Attention is currently required from: Hung-Te Lin, Yu-Ping Wu.
Yidi Lin has posted comments on this change by Yidi Lin. ( https://review.coreboot.org/c/coreboot/+/85861?usp=email )
Change subject: soc/mediatek/common/dp: Move common functions to dptx_hal_common.c ......................................................................
Patch Set 7:
(6 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85861/comment/2cecacdc_080f0839?usp... : PS3, Line 11: Adding
Add
Removed
https://review.coreboot.org/c/coreboot/+/85861/comment/28418833_bf74ebe5?usp... : PS3, Line 12: underly
underlying?
Removed
File src/soc/mediatek/common/dp/dptx_hal.c:
https://review.coreboot.org/c/coreboot/+/85861/comment/591d7524_f72c5938?usp... : PS3, Line 339: 0xfff
Not related to this patch, but this looks like a bug. […]
CB:85918
File src/soc/mediatek/common/dp/dptx_hal_common.c:
https://review.coreboot.org/c/coreboot/+/85861/comment/47e03bfd_185cf400?usp... : PS3, Line 56: u32
Unrelated to this patch, but this should be `u8`.
CB:85917
https://review.coreboot.org/c/coreboot/+/85861/comment/0053bf2a_727386a7?usp... : PS3, Line 115: DP_CLRSETBITS(mtk_dp, REG_303C_DP_ENCODER0_P0 + 1, val, 0x7);
Great! That makes a lot of sense.
Done
https://review.coreboot.org/c/coreboot/+/85861/comment/5cc255f7_c8c52564?usp... : PS3, Line 143: DP_CLRSETBITS(mtk_dp, REG_3004_DP_ENCODER0_P0 + 1,
Same here.
Done