Brandon Weeks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81595?usp=email )
Change subject: mb/cwwk: Add CWWK CW-ADL-4L-V2.0 board ......................................................................
mb/cwwk: Add CWWK CW-ADL-4L-V2.0 board
Change-Id: Ice9174d95c10afc6a22ddd15fb3be4fa38d329be Signed-off-by: Brandon Weeks me@brandonweeks.com --- A src/mainboard/cwwk/Kconfig A src/mainboard/cwwk/Kconfig.name A src/mainboard/cwwk/adl/Kconfig A src/mainboard/cwwk/adl/Kconfig.name A src/mainboard/cwwk/adl/Makefile.inc A src/mainboard/cwwk/adl/board.fmd A src/mainboard/cwwk/adl/board_info.txt A src/mainboard/cwwk/adl/bootblock.c A src/mainboard/cwwk/adl/data.vbt A src/mainboard/cwwk/adl/devicetree.cb A src/mainboard/cwwk/adl/dsdt.asl A src/mainboard/cwwk/adl/gpio.h A src/mainboard/cwwk/adl/mainboard.c A src/mainboard/cwwk/adl/romstage_fsp_params.c 14 files changed, 561 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/81595/1
diff --git a/src/mainboard/cwwk/Kconfig b/src/mainboard/cwwk/Kconfig new file mode 100644 index 0000000..ccbe902 --- /dev/null +++ b/src/mainboard/cwwk/Kconfig @@ -0,0 +1,15 @@ +if VENDOR_CWWK + +choice + prompt "Mainboard model" + +source "src/mainboard/cwwk/*/Kconfig.name" + +endchoice + +source "src/mainboard/cwwk/*/Kconfig" + +config MAINBOARD_VENDOR + default "CWWK" + +endif # VENDOR_CWWK diff --git a/src/mainboard/cwwk/Kconfig.name b/src/mainboard/cwwk/Kconfig.name new file mode 100644 index 0000000..5262d06 --- /dev/null +++ b/src/mainboard/cwwk/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_CWWK + bool "CWWK" diff --git a/src/mainboard/cwwk/adl/Kconfig b/src/mainboard/cwwk/adl/Kconfig new file mode 100644 index 0000000..3a5d064 --- /dev/null +++ b/src/mainboard/cwwk/adl/Kconfig @@ -0,0 +1,40 @@ +if BOARD_CWWK_ADL_N + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select DRIVERS_UART_8250IO + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select SOC_INTEL_ALDERLAKE_PCH_N + select SUPERIO_ITE_IT8613E + +config MAINBOARD_DIR + default "cwwk/adl" + +config MAINBOARD_PART_NUMBER + default "CW-AL-4L-V1.0" + +config DEVICETREE + default "devicetree.cb" + +config DIMM_MAX + default 2 + +config DIMM_SPD_SIZE + default 512 + +config FMDFILE + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd" + +config NO_POST + default y + +config USE_PM_ACPI_TIMER + default n + +config EDK2_BOOT_TIMEOUT + default 5 + +endif diff --git a/src/mainboard/cwwk/adl/Kconfig.name b/src/mainboard/cwwk/adl/Kconfig.name new file mode 100644 index 0000000..6b0ce7c --- /dev/null +++ b/src/mainboard/cwwk/adl/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_CWWK_ADL_N + bool "CW-ADL-4L-V1.0" diff --git a/src/mainboard/cwwk/adl/Makefile.inc b/src/mainboard/cwwk/adl/Makefile.inc new file mode 100644 index 0000000..89eb072db --- /dev/null +++ b/src/mainboard/cwwk/adl/Makefile.inc @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +bootblock-y += bootblock.c + +romstage-y += romstage_fsp_params.c + +ramstage-y += mainboard.c diff --git a/src/mainboard/cwwk/adl/board.fmd b/src/mainboard/cwwk/adl/board.fmd new file mode 100644 index 0000000..b305b9b --- /dev/null +++ b/src/mainboard/cwwk/adl/board.fmd @@ -0,0 +1,13 @@ +FLASH 16M { + SI_ALL 6M { + SI_DESC 4K + SI_ME 4172K + SI_DEVICEEXT2 + } + SI_BIOS 10M { + RW_MRC_CACHE 64K + SMMSTORE(PRESERVE) 256K + FMAP 4K + COREBOOT(CBFS) + } +} diff --git a/src/mainboard/cwwk/adl/board_info.txt b/src/mainboard/cwwk/adl/board_info.txt new file mode 100644 index 0000000..b53863c --- /dev/null +++ b/src/mainboard/cwwk/adl/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: CWWK +Board name: CW-ADL-4L-V1.0 +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/cwwk/adl/bootblock.c b/src/mainboard/cwwk/adl/bootblock.c new file mode 100644 index 0000000..f19b383 --- /dev/null +++ b/src/mainboard/cwwk/adl/bootblock.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <bootblock_common.h> +#include <superio/ite/common/ite.h> +#include <superio/ite/it8613e/it8613e.h> + +#define UART_DEV PNP_DEV(0x2e, IT8613E_SP1) + +void bootblock_mainboard_early_init(void) +{ + ite_enable_serial(UART_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/cwwk/adl/data.vbt b/src/mainboard/cwwk/adl/data.vbt new file mode 100644 index 0000000..2a6c207 --- /dev/null +++ b/src/mainboard/cwwk/adl/data.vbt Binary files differ diff --git a/src/mainboard/cwwk/adl/devicetree.cb b/src/mainboard/cwwk/adl/devicetree.cb new file mode 100644 index 0000000..b933a94 --- /dev/null +++ b/src/mainboard/cwwk/adl/devicetree.cb @@ -0,0 +1,91 @@ +chip soc/intel/alderlake + + register "s0ix_enable" = "1" + + # TODO: disable audio + #register "DspEnable" = "0" + + register "usb2_ports[0]" = "USB2_PORT_SHORT(OC_SKIP)" + register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)" + register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)" + register "usb2_ports[3]" = "USB2_PORT_SHORT(OC_SKIP)" + register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" # microSD card reader + + register "pch_pcie_rp[PCH_RP(1)]" = "{ + .clk_src = 0, + .clk_req = 0, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + + register "pch_pcie_rp[PCH_RP(7)]" = "{ + .clk_src = 1, + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN, + .pcie_rp_aspm = ASPM_DISABLE, + }" + + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .clk_src = 2, + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN, + .pcie_rp_aspm = ASPM_DISABLE, + }" + + register "pch_pcie_rp[PCH_RP(10)]" = "{ + .clk_src = 3, + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN, + .pcie_rp_aspm = ASPM_DISABLE, + }" + + register "pch_pcie_rp[PCH_RP(11)]" = "{ + .clk_src = 4, + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN, + .pcie_rp_aspm = ASPM_DISABLE, + }" + + register "pch_pcie_rp[PCH_RP(12)]" = "{ + .clk_src = 5, + .clk_req = 5, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + + # Enable EDP in PortA + register "ddi_portA_config" = "1" + + # Enable HDMI in Port B + # register "ddi_ports_config" = "{ + # [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + # }" + + device domain 0 on + device ref igpu on end + device ref dtt on end + device ref crashlog off end + device ref xhci on end + device ref shared_sram on end + device ref heci1 on end + device ref emmc off end + device ref pcie_rp1 on end + device ref pcie_rp7 on end + device ref pcie_rp9 on end + device ref pcie_rp10 on end + device ref pcie_rp11 on end + device ref pcie_rp12 on end # M.2 E key port + device ref pch_espi on + chip superio/ite/it8613e + device pnp 2e.0 off end + device pnp 2e.1 on # COM 1 + io 0x60 = 0x3f8 + irq 0x70 = 0x4 + irq 0xf0 = 0x1 + end + device pnp 2e.4 off end # Environment Controller + device pnp 2e.5 off end # Keyboard + device pnp 2e.6 off end # Mouse + device pnp 2e.7 off end # GPIO + device pnp 2e.a off end # CIR + end + end + device ref hda on end + device ref smbus on end + end +end + diff --git a/src/mainboard/cwwk/adl/dsdt.asl b/src/mainboard/cwwk/adl/dsdt.asl new file mode 100644 index 0000000..e612ec0 --- /dev/null +++ b/src/mainboard/cwwk/adl/dsdt.asl @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include <acpi/dsdt_top.asl> + #include <soc/intel/common/block/acpi/acpi/platform.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + #include <cpu/intel/common/acpi/cpu.asl> + + Device (_SB.PCI0) { + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/alderlake/acpi/southbridge.asl> + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> +} diff --git a/src/mainboard/cwwk/adl/gpio.h b/src/mainboard/cwwk/adl/gpio.h new file mode 100644 index 0000000..fc3d7ea --- /dev/null +++ b/src/mainboard/cwwk/adl/gpio.h @@ -0,0 +1,297 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef CFG_GPIO_H +#define CFG_GPIO_H + +#include <soc/gpio.h> + +/* Pad configuration was generated automatically using intelp2m utility */ +static const struct pad_config gpio_table[] = { + + /* ------- GPIO Community 0 ------- */ + + /* ------- GPIO Group GPP_B ------- */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), /* CORE_VID0 */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), /* CORE_VID1 */ + PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), /* VRALERT# */ + PAD_NC(GPP_B3, NONE), /* GPIO */ + PAD_NC(GPP_B4, NONE), /* GPIO */ + PAD_NC(GPP_B5, NONE), /* GPIO */ + PAD_NC(GPP_B6, NONE), /* GPIO */ + PAD_NC(GPP_B7, NONE), /* GPIO */ + PAD_NC(GPP_B8, NONE), /* GPIO */ + PAD_NC(GPP_B9, NONE), /* GPIO */ + PAD_NC(GPP_B10, NONE), /* GPIO */ + //PAD_CFG_NF(GPP_B11, NONE, RSMRST, NF1), /* PMCALERT# */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* SLP_S0# */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PLTRST# */ + PAD_CFG_GPO(GPP_B14, 0, PLTRST), /* GPIO */ + PAD_NC(GPP_B15, NONE), /* GPIO */ + PAD_NC(GPP_B16, NONE), /* GPIO */ + PAD_NC(GPP_B17, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_B18, 0, PLTRST), /* GPIO */ + PAD_NC(GPP_B19, NONE), /* GPIO */ + PAD_NC(GPP_B20, NONE), /* GPIO */ + PAD_NC(GPP_B21, NONE), /* GPIO */ + PAD_NC(GPP_B22, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_B23, 1, PLTRST), /* GPIO */ + PAD_CFG_NF(GPP_B24, NONE, DEEP, NF1), /* GSPI0_CLK_LOOPBK */ + PAD_CFG_NF(GPP_B25, NONE, DEEP, NF1), /* GSPI1_CLK_LOOPBK */ + + /* ------- GPIO Group GPP_T ------- */ + PAD_NC(GPP_T0, NONE), /* GPIO */ + PAD_NC(GPP_T1, NONE), /* GPIO */ + PAD_CFG_NF(GPP_T2, DN_20K, DEEP, NF2), /* FUSA_DIAGTEST_EN */ + PAD_CFG_NF(GPP_T3, DN_20K, DEEP, NF2), /* FUSA_DIAGTEST_MODE */ + PAD_NC(GPP_T4, NONE), /* GPIO */ + PAD_NC(GPP_T5, NONE), /* GPIO */ + PAD_NC(GPP_T6, NONE), /* GPIO */ + PAD_NC(GPP_T7, NONE), /* GPIO */ + PAD_NC(GPP_T8, NONE), /* GPIO */ + PAD_NC(GPP_T9, NONE), /* GPIO */ + PAD_NC(GPP_T10, NONE), /* GPIO */ + PAD_NC(GPP_T11, NONE), /* GPIO */ + PAD_NC(GPP_T12, NONE), /* GPIO */ + PAD_NC(GPP_T13, NONE), /* GPIO */ + PAD_NC(GPP_T14, NONE), /* GPIO */ + PAD_NC(GPP_T15, NONE), /* GPIO */ + + /* ------- GPIO Group GPP_A ------- */ + PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), /* ESPI_IO0 */ + PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), /* ESPI_IO1 */ + PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), /* ESPI_IO2 */ + PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), /* ESPI_IO3 */ + PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), /* ESPI_CS0# */ + PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1), /* ESPI_ALERT0# */ + PAD_CFG_NF(GPP_A6, UP_20K, DEEP, NF1), /* ESPI_ALERT1# */ + PAD_CFG_GPO(GPP_A7, 1, PLTRST), /* GPIO */ + PAD_NC(GPP_A8, NONE), /* GPIO */ + PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), /* ESPI_CLK */ + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), /* ESPI_RESET# */ + PAD_NC(GPP_A11, NONE), /* GPIO */ + PAD_NC(GPP_A12, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_A13, 1, DEEP), /* GPIO */ + PAD_NC(GPP_A14, NONE), /* GPIO */ + PAD_NC(GPP_A15, NONE), /* GPIO */ + PAD_NC(GPP_A16, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_A17, 1, PLTRST), /* GPIO */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), /* DDSP_HPDB */ + PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), /* DDSP_HPD1 */ + PAD_NC(GPP_A20, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_A21, 1, PLTRST), /* GPIO */ + PAD_NC(GPP_A22, NONE), /* GPIO */ + PAD_CFG_NF(GPP_A23, UP_20K, DEEP, NF1), /* ESPI_CS1# */ + PAD_CFG_NF(GPP_ESPI_CLK_LOOPBK, NONE, DEEP, NF1), /* GPP_ESPI_CLK_LOOPBK */ + + /* ------- GPIO Community 1 ------- */ + + /* ------- GPIO Group GPP_S ------- */ + PAD_NC(GPP_S0, NONE), /* GPIO */ + PAD_NC(GPP_S1, NONE), /* GPIO */ + PAD_NC(GPP_S2, NONE), /* GPIO */ + PAD_NC(GPP_S3, NONE), /* GPIO */ + PAD_NC(GPP_S4, NONE), /* GPIO */ + PAD_NC(GPP_S5, NONE), /* GPIO */ + PAD_NC(GPP_S6, NONE), /* GPIO */ + PAD_NC(GPP_S7, NONE), /* GPIO */ + + /* ------- GPIO Group GPP_I ------- */ + PAD_NC(GPP_I0, NONE), /* GPIO */ + PAD_NC(GPP_I1, NONE), /* GPIO */ + PAD_NC(GPP_I2, NONE), /* GPIO */ + PAD_NC(GPP_I3, NONE), /* GPIO */ + PAD_NC(GPP_I4, NONE), /* GPIO */ + PAD_NC(GPP_I5, NONE), /* GPIO */ + PAD_NC(GPP_I6, NONE), /* GPIO */ + PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), /* EMMC_CMD */ + PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), /* EMMC_DATA0 */ + PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1), /* EMMC_DATA1 */ + PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1), /* EMMC_DATA2 */ + PAD_CFG_NF(GPP_I11, NONE, DEEP, NF1), /* EMMC_DATA3 */ + PAD_CFG_NF(GPP_I12, NONE, DEEP, NF1), /* EMMC_DATA4 */ + PAD_CFG_NF(GPP_I13, NONE, DEEP, NF1), /* EMMC_DATA5 */ + PAD_CFG_NF(GPP_I14, NONE, DEEP, NF1), /* EMMC_DATA6 */ + PAD_CFG_NF(GPP_I15, NONE, DEEP, NF1), /* EMMC_DATA7 */ + PAD_CFG_NF(GPP_I16, NONE, DEEP, NF1), /* EMMC_RCLK */ + PAD_CFG_NF(GPP_I17, NONE, DEEP, NF1), /* EMMC_CLK */ + PAD_CFG_NF(GPP_I18, NONE, DEEP, NF1), /* EMMC_RESET# */ + PAD_NC(GPP_I19, NONE), /* GPIO */ + + /* ------- GPIO Group GPP_H ------- */ + PAD_CFG_GPO(GPP_H0, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_H1, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_H2, 1, RSMRST), /* GPIO */ + PAD_NC(GPP_H3, NONE), /* GPIO */ + PAD_NC(GPP_H4, NONE), /* GPIO */ + PAD_NC(GPP_H5, NONE), /* GPIO */ + PAD_NC(GPP_H6, NONE), /* GPIO */ + PAD_NC(GPP_H7, NONE), /* GPIO */ + PAD_NC(GPP_H8, NONE), /* GPIO */ + PAD_NC(GPP_H9, NONE), /* GPIO */ + PAD_NC(GPP_H10, NONE), /* GPIO */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* UART0_TXD */ + PAD_NC(GPP_H12, NONE), /* GPIO */ + PAD_NC(GPP_H13, NONE), /* GPIO */ + PAD_NC(GPP_H14, NONE), /* GPIO */ + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), /* DDPB_CTRLCLK */ + PAD_NC(GPP_H16, NONE), /* GPIO */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), /* DDPB_CTRLDATA */ + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), /* PROC_C10_GATE# */ + PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), /* SRCCLKREQ4# */ + PAD_NC(GPP_H20, NONE), /* GPIO */ + PAD_NC(GPP_H21, NONE), /* GPIO */ + PAD_NC(GPP_H22, NONE), /* GPIO */ + PAD_NC(GPP_H23, NONE), /* GPIO */ + + /* ------- GPIO Group GPP_D ------- */ + PAD_NC(GPP_D0, NONE), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D1, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_NC(GPP_D2, NONE), /* GPIO */ + PAD_NC(GPP_D3, NONE), /* GPIO */ + PAD_NC(GPP_D4, NONE), /* GPIO */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), /* SRCCLKREQ0# */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), /* SRCCLKREQ1# */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), /* SRCCLKREQ2# */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), /* SRCCLKREQ3# */ + PAD_CFG_NF(GPP_D9, NATIVE, DEEP, NF5), /* BSSB_LS2_RX */ + PAD_CFG_NF(GPP_D10, NATIVE, DEEP, NF5), /* BSSB_LS2_TX */ + PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF5), /* BSSB_LS3_RX */ + PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF5), /* BSSB_LS3_TX */ + PAD_NC(GPP_D13, NONE), /* GPIO */ + PAD_NC(GPP_D14, NONE), /* GPIO */ + PAD_NC(GPP_D15, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_D16, 1, PLTRST), /* GPIO */ + PAD_NC(GPP_D17, NONE), /* GPIO */ + PAD_NC(GPP_D18, NONE), /* GPIO */ + PAD_NC(GPP_D19, NONE), /* GPIO */ + PAD_CFG_NF(GPP_GSPI2_CLK_LOOPBK, NONE, DEEP, NF1), /* GPP_GSPI2_CLK_LOOPBK */ + + /* ------- GPIO Group vGPIO ------- */ + + /* ------- GPIO Community 2 ------- */ + + /* ------- GPIO Group GPP_GPD ------- */ + PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), /* BATLOW# */ + PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), /* ACPRESENT */ + PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), /* LAN_WAKE# */ + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), /* PWRBTN# */ + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), /* SLP_S3# */ + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), /* SLP_S4# */ + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), /* SLP_A# */ + PAD_CFG_GPO(GPD7, 0, PWROK), /* GPIO */ + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), /* SUSCLK */ + PAD_CFG_NF(GPD9, NONE, PWROK, NF1), /* SLP_WLAN# */ + PAD_CFG_NF(GPD10, NONE, PWROK, NF1), /* SLP_S5# */ + PAD_CFG_GPO(GPD11, 0, PWROK), /* GPIO */ + PAD_CFG_NF(GPD_INPUT3VSEL, NONE, PWROK, NF1), /* GPD_INPUT3VSEL */ + PAD_CFG_NF(GPD_SLP_LANB, NONE, PWROK, NF1), /* GPD_SLP_LANB */ + PAD_CFG_NF(GPD_SLP_SUSB, NONE, PWROK, NF1), /* GPD_SLP_SUSB */ + PAD_CFG_NF(GPD_WAKEB, NONE, PWROK, NF1), /* GPD_WAKEB */ + PAD_CFG_NF(GPD_DRAM_RESETB, NONE, PWROK, NF1), /* GPD_DRAM_RESETB */ + + /* ------- GPIO Group PCIe vGPIO ------- */ + + /* ------- GPIO Community 4 ------- */ + + /* ------- GPIO Group GPP_C ------- */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMBCLK */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMBDATA */ + PAD_CFG_GPO(GPP_C2, 0, DEEP), /* GPIO */ + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0CLK */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0DATA */ + PAD_CFG_GPO(GPP_C5, 0, DEEP), /* GPIO */ + PAD_CFG_NF(GPP_C6, NONE, RSMRST, NF1), /* SML1CLK */ + PAD_CFG_NF(GPP_C7, NONE, RSMRST, NF1), /* SML1DATA */ + PAD_NC(GPP_C8, NONE), /* GPIO */ + PAD_NC(GPP_C9, NONE), /* GPIO */ + PAD_NC(GPP_C10, NONE), /* GPIO */ + PAD_NC(GPP_C11, NONE), /* GPIO */ + PAD_NC(GPP_C12, NONE), /* GPIO */ + PAD_NC(GPP_C13, NONE), /* GPIO */ + PAD_NC(GPP_C14, NONE), /* GPIO */ + PAD_NC(GPP_C15, NONE), /* GPIO */ + PAD_NC(GPP_C16, NONE), /* GPIO */ + PAD_NC(GPP_C17, NONE), /* GPIO */ + PAD_NC(GPP_C18, NONE), /* GPIO */ + PAD_NC(GPP_C19, NONE), /* GPIO */ + PAD_NC(GPP_C20, NONE), /* GPIO */ + PAD_NC(GPP_C21, NONE), /* GPIO */ + PAD_NC(GPP_C22, NONE), /* GPIO */ + PAD_NC(GPP_C23, NONE), /* GPIO */ + + /* ------- GPIO Group GPP_F ------- */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), /* CNV_BRI_DT */ + PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), /* CNV_BRI_RSP */ + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), /* CNV_RGI_DT */ + PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), /* CNV_RGI_RSP */ + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* CNV_RF_RESET# */ + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2), /* MODEM_CLKREQ */ + PAD_NC(GPP_F6, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_F7, 0, DEEP), /* GPIO */ + PAD_NC(GPP_F8, NONE), /* GPIO */ + PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* BOOTMPC */ + PAD_CFG_GPO(GPP_F10, 1, PLTRST), /* GPIO */ + PAD_NC(GPP_F11, NONE), /* GPIO */ + PAD_NC(GPP_F12, NONE), /* GPIO */ + PAD_NC(GPP_F13, NONE), /* GPIO */ + PAD_NC(GPP_F14, NONE), /* GPIO */ + PAD_NC(GPP_F15, NONE), /* GPIO */ + PAD_NC(GPP_F16, NONE), /* GPIO */ + PAD_NC(GPP_F17, NONE), /* GPIO */ + PAD_NC(GPP_F18, NONE), /* GPIO */ + PAD_NC(GPP_F19, NONE), /* GPIO */ + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), /* Reserved */ + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* Reserved */ + PAD_NC(GPP_F22, NONE), /* GPIO */ + PAD_NC(GPP_F23, NONE), /* GPIO */ + PAD_NC(GPP_F_CLK_LOOPBK, NONE), /* GPIO */ + + /* ------- GPIO Group GPP_HVCMOS ------- */ + PAD_CFG_NF(GPP_L_BKLTEN, NONE, DEEP, NF1), /* n/a */ + PAD_CFG_NF(GPP_L_BKLTCTL, NONE, DEEP, NF1), /* n/a */ + PAD_CFG_NF(GPP_L_VDDEN, NONE, DEEP, NF1), /* n/a */ + PAD_CFG_NF(GPP_SYS_PWROK, NONE, DEEP, NF1), /* n/a */ + PAD_CFG_NF(GPP_SYS_RESETB, NONE, DEEP, NF1), /* n/a */ + PAD_CFG_NF(GPP_MLK_RSTB, NONE, DEEP, NF1), /* n/a */ + + /* ------- GPIO Group GPP_E ------- */ + PAD_NC(GPP_E0, NONE), /* GPIO */ + PAD_NC(GPP_E1, NONE), /* GPIO */ + PAD_NC(GPP_E2, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_E3, 1, DEEP), /* GPIO */ + PAD_NC(GPP_E4, NONE), /* GPIO */ + PAD_NC(GPP_E5, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_E6, 0, DEEP), /* GPIO */ + PAD_NC(GPP_E7, NONE), /* GPIO */ + PAD_NC(GPP_E8, NONE), /* GPIO */ + PAD_NC(GPP_E9, NONE), /* GPIO */ + PAD_NC(GPP_E10, NONE), /* GPIO */ + PAD_NC(GPP_E11, NONE), /* GPIO */ + PAD_NC(GPP_E12, NONE), /* GPIO */ + PAD_NC(GPP_E13, NONE), /* GPIO */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDSP_HPDA */ + PAD_CFG_GPO(GPP_E15, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_E16, 0, PLTRST), /* GPIO */ + PAD_NC(GPP_E17, NONE), /* GPIO */ + PAD_CFG_NF(GPP_E18, NATIVE, DEEP, NF5), /* BSSB_LS0_RX */ + PAD_CFG_NF(GPP_E19, NATIVE, DEEP, NF5), /* BSSB_LS0_TX */ + PAD_CFG_GPO(GPP_E20, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_E21, 0, PLTRST), /* GPIO */ + PAD_CFG_NF(GPP_E22, DN_20K, DEEP, NF1), /* DDPA_CTRLCLK */ + PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1), /* DDPA_CTRLDATA */ + PAD_NC(GPP_E_CLK_LOOPBK, NONE), /* GPIO */ + + /* ------- GPIO Community 5 ------- */ + + /* ------- GPIO Group GPP_R ------- */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), /* HDA_BCLK */ + PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), /* HDA_SYNC */ + PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), /* HDA_SDO */ + PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), /* HDA_SDI0 */ + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), /* HDA_RST# */ + PAD_NC(GPP_R5, NONE), /* GPIO */ + PAD_NC(GPP_R6, NONE), /* GPIO */ + PAD_NC(GPP_R7, NONE), /* GPIO */ +}; + +#endif /* CFG_GPIO_H */ diff --git a/src/mainboard/cwwk/adl/mainboard.c b/src/mainboard/cwwk/adl/mainboard.c new file mode 100644 index 0000000..439661d --- /dev/null +++ b/src/mainboard/cwwk/adl/mainboard.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <soc/ramstage.h> +#include "gpio.h" + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + params->PchEspiLgmrEnable = 0; +} + +static void mainboard_init(void *chip_info) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, +}; diff --git a/src/mainboard/cwwk/adl/romstage_fsp_params.c b/src/mainboard/cwwk/adl/romstage_fsp_params.c new file mode 100644 index 0000000..614c9f5 --- /dev/null +++ b/src/mainboard/cwwk/adl/romstage_fsp_params.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <fsp/api.h> +#include <soc/meminit.h> +#include <soc/romstage.h> + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + static const struct mb_cfg ddr5_mem_config = { + .type = MEM_TYPE_DDR5, + + .ect = true, /* Early Command Training */ + + .UserBd = BOARD_TYPE_MOBILE, + + .LpDdrDqDqsReTraining = 1, + }; + + const struct mem_spd dimm_module_spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { + .addr_dimm[0] = 0x50, + }, + [1] = { + .addr_dimm[0] = 0x52, + }, + }, + }; + + const bool half_populated = false; + memcfg_init(memupd, &ddr5_mem_config, &dimm_module_spd_info, half_populated); +}