[coreboot-gerrit] Change in coreboot[master]: src/soc/tigerlake: Add memory configuration support for Jasper Lake

[Karthik Ramasubramanian (Code Review)]

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39135 )

Change subject: src/soc/tigerlake: Add memory configuration support for Jasper Lake
......................................................................

Patch Set 21:

(1 comment)

https://review.coreboot.org/c/coreboot/+/39135/14/src/soc/intel/tigerlake/in... 
File src/soc/intel/tigerlake/include/soc/meminit_jsl.h:

https://review.coreboot.org/c/coreboot/+/39135/14/src/soc/intel/tigerlake/in... 
PS14, Line 132: )
> Okay. But Furquan, I am not understanding the direction here. […]

Meera, Furquan articulated exactly what I was referring to. In the past for pricing reasons, memory has been populated on only one channels by OEMs - eg. Octopus and Hatch. The performance was not too bad in those situations.