[coreboot-gerrit] Change in ...coreboot[master]: src/soc/intel/cannonlake: [TEST-ONLY]Update FSP-M upd config for cml

[Aamir Bohra (Code Review)]

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32767

Change subject: src/soc/intel/cannonlake: [TEST-ONLY]Update FSP-M upd config for cml
......................................................................

src/soc/intel/cannonlake: [TEST-ONLY]Update FSP-M upd config for cml

This patch updates the fsp-m config for cometlake platform.
The FSP release from version 1155 onwards have updated fsp-m config
for UART controller number used for debug logs purpose.

Change-Id: I232630f91ba6bbc953064bddab7cf0e479510fc9
Signed-off-by: Aamir Bohra 
---
M src/soc/intel/cannonlake/romstage/fsp_params.c
1 file changed, 4 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/32767/1

diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
index 6e492bb..77bad8f 100644
--- a/src/soc/intel/cannonlake/romstage/fsp_params.c
+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -50,7 +50,11 @@
    m_cfg->PcieRpEnableMask = mask;
    m_cfg->PrmrrSize = config->PrmrrSize;
    m_cfg->EnableC6Dram = config->enable_c6dram;
+#if CONFIG(SOC_INTEL_COMETLAKE)
+	m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE;
+#else
    m_cfg->PcdSerialIoUartNumber = CONFIG_UART_FOR_CONSOLE;
+#endif
    /*
     * PcdDebugInterfaceFlags
     * This config will allow coreboot to pass information to the FSP