[coreboot-gerrit] Change in coreboot[master]: soc/intel/jasperlake: Add a workaround for cnvi

[Jamie Chen (Code Review)]

Attention is currently required from: Jamie Chen, Tim Wawrzynczak, Karthik Ramasubramanian.
Hello build bot (Jenkins), Subrata Banik, Tim Wawrzynczak, Tim Wawrzynczak, Karthik Ramasubramanian,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/63675

to look at the new patch set (#3).

Change subject: soc/intel/jasperlake: Add a workaround for cnvi
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soc/intel/jasperlake: Add a workaround for cnvi

According to Intel TA#724456, add a workaround to mitigate
the higher SoC power consumption in S0iX when CNVI has background
activity.

BUG=b:201263040
TEST=Turn on this setting and build and verify on Drawcia.
     Those settings are correct.

Change-Id: I56439a406547e2ee1e47d34be14ecc9a8df04693
Signed-off-by: Jamie Chen 
---
M src/soc/intel/jasperlake/chip.h
M src/soc/intel/jasperlake/finalize.c
M src/soc/intel/jasperlake/include/soc/pmc.h
3 files changed, 22 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/63675/3