Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34120 )
Change subject: soc/intel/{cannonlake,icelake}: Do not define PCH_DEV_PMC in ramstage
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Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34120/2//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/34120/2//COMMIT_MSG@10
PS2, Line 10: This device gets hidden from PCI bus
: in FSP-S
Small question: Is this because of POSTBOOT_SAI?
No, in SPT PCH, PWRMBASE and ABASE are at offset 0x44 and 0x48 hence PCI enumeration don't change the predefined base addresses.
But in CNP PCH onwards, PWRMBASE and ABASE are located in offset 0x10 and 0x20 which is part of standard PCI BARs. Hence allowing PCI device available during PCI enumeration might allow it to override those pre-defined values. hence its been recommended that PMC device gets hidden from PCI tree and hold its pre-programmed value.
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