Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38691 )
Change subject: soc/amd/picasso: Enable cache in bootblock ......................................................................
Patch Set 4:
(3 comments)
https://review.coreboot.org/c/coreboot/+/38691/2/src/soc/amd/picasso/bootblo... File src/soc/amd/picasso/bootblock/bootblock.c:
https://review.coreboot.org/c/coreboot/+/38691/2/src/soc/amd/picasso/bootblo... PS2, Line 58: SYSCFG_MSR_MtrrFixDramEn
What does this exactly do?
1=Enables the RdDram and WrDram attributes in Core::X86::Msr::MtrrFix_64K through Core::X86::Msr::MtrrFix_4K_7.
Not sure why it's being turned off.
https://review.coreboot.org/c/coreboot/+/38691/2/src/soc/amd/picasso/bootblo... PS2, Line 66: get_free_var_mtrr() The PPR says:
Valid: Read-write. Reset: X. 1=The variable-size MTRR pair is enabled.
Looks like it's undefined.
https://review.coreboot.org/c/coreboot/+/38691/2/src/soc/amd/picasso/bootblo... PS2, Line 69: CONFIG_ROM_SIZE
What if CONFIG_ROM_SIZE is >16MiB?
47:12 PhyMask: address mask. Read-write. Reset: X_XXXX_XXXXh.
I think that's plenty of bits.