[coreboot-gerrit] Change in coreboot[master]: mb/asus/kgpe-d16/bootblock.c: Refactor mainboard bootblock init

[Michał Żygowski (Code Review)]

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62113 )

Change subject: mb/asus/kgpe-d16/bootblock.c: Refactor mainboard bootblock init
......................................................................

mb/asus/kgpe-d16/bootblock.c: Refactor mainboard bootblock init

Signed-off-by: Michał Żygowski 
Change-Id: I694cd72f3641ddcf82710709672e14961d336d3b
---
M src/mainboard/asus/kgpe-d16/Makefile.inc
M src/mainboard/asus/kgpe-d16/bootblock.c
2 files changed, 50 insertions(+), 21 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/62113/1

diff --git a/src/mainboard/asus/kgpe-d16/Makefile.inc b/src/mainboard/asus/kgpe-d16/Makefile.inc
index eb6e528..c5f03ec 100644
--- a/src/mainboard/asus/kgpe-d16/Makefile.inc
+++ b/src/mainboard/asus/kgpe-d16/Makefile.inc
@@ -10,3 +10,5 @@
 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 # GNU General Public License for more details.
 #
+
+bootblock-y += bootblock.c
diff --git a/src/mainboard/asus/kgpe-d16/bootblock.c b/src/mainboard/asus/kgpe-d16/bootblock.c
index 543ffed..7645933 100644
--- a/src/mainboard/asus/kgpe-d16/bootblock.c
+++ b/src/mainboard/asus/kgpe-d16/bootblock.c
@@ -15,38 +15,65 @@
  * GNU General Public License for more details.
  */

+#include <bootblock_common.h>
+#include <console/console.h>
 #include <device/pci_ops.h>
 #include <pc80/mc146818rtc.h>
+#include <superio/winbond/common/winbond.h>
+#include <superio/winbond/w83667hg-a/w83667hg-a.h>
+#include <option_table.h>

-void bootblock_mainboard_init(void)
+#define SERIAL_0_DEV PNP_DEV(0x2e, W83667HG_A_SP1)
+#define SERIAL_1_DEV PNP_DEV(0x2e, W83667HG_A_SP2)
+
+static bool mainboard_get_recovery_state(void)
 {
-	uint8_t recovery_enabled;
-	unsigned char addr;
-	unsigned char byte;
-
-	bootblock_northbridge_init();
-	bootblock_southbridge_init();
-
-	/* Recovery jumper is connected to SP5100 GPIO61, and clears the GPIO when placed in the Recovery position */
-	byte = pci_io_read_config8(PCI_DEV(0, 0x14, 0), 0x56);
+	u8 byte;
+	pci_devfn_t dev = PCI_DEV(0, 0x14, 0);
+	/*
+	 * Recovery jumper is connected to SP5100 GPIO61, and clears the GPIO
+	 * when placed in the Recovery position
+	 */
+	byte = pci_read_config8(dev, 0x56);
    byte |= 0x1 << 4;	/*  Set GPIO61 to input mode */
-	pci_io_write_config8(PCI_DEV(0, 0x14, 0), 0x56, byte);
-	recovery_enabled = (!(pci_io_read_config8(PCI_DEV(0, 0x14, 0), 0x57) & 0x1));
-	if (recovery_enabled) {
-#if CONFIG(USE_OPTION_TABLE)
+	pci_write_config8(dev, 0x56, byte);
+	return !(pci_read_config8(dev, 0x57) & 0x1);
+}
+
+void bootblock_mainboard_early_init(void)
+{
+	u8 addr, byte;
+
+	/* Configure secondary serial port pin mux */
+	winbond_set_pinmux(SERIAL_1_DEV, 0x2a,
+			   W83667HG_SPI_PINMUX_GPIO4_SERIAL_B_MASK,
+			   W83667HG_SPI_PINMUX_SERIAL_B);
+
+	/* Initialize early serial */
+	winbond_enable_serial(SERIAL_0_DEV, CONFIG_TTYS0_BASE);
+
+	if (mainboard_get_recovery_state() && CONFIG(USE_OPTION_TABLE)) {
    	/* Clear NVRAM checksum */
-		for (addr = LB_CKS_RANGE_START; addr <= LB_CKS_RANGE_END; addr++) {
+		for (addr = LB_CKS_RANGE_START; addr <= LB_CKS_RANGE_END; addr++)
    		cmos_write(0x0, addr);
-		}

/* Set fallback boot */
    	byte = cmos_read(RTC_BOOT_BYTE);
    	byte &= 0xfc;
    	cmos_write(byte, RTC_BOOT_BYTE);
-#else
-		/* FIXME
-		 * Figure out how to recover if the option table is not available
-		 */
-#endif
+	}
+}
+
+void bootblock_mainboard_init(void)
+{
+	if (mainboard_get_recovery_state()) {
+		if (CONFIG(USE_OPTION_TABLE)) {
+			printk(BIOS_INFO, "Recovery requested, CMOS has been cleared\n");
+		} else {
+			/*
+			 * FIXME Figure out how to recover if the option table is not available
+			 */
+			printk(BIOS_INFO, "Recovery requested but option table not enabled\n");
+		}
    }
 }