[coreboot-gerrit] [M] Change in coreboot[master]: soc/intel/meteorlake: Refactor `pmc_lockdown_cfg` function

[Kapil Porwal (Code Review)]

Kapil Porwal has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70132 )

Change subject: soc/intel/meteorlake: Refactor `pmc_lockdown_cfg` function
......................................................................

soc/intel/meteorlake: Refactor `pmc_lockdown_cfg` function

This patch refactors the `pmc_lockdown_cfg()` to remove the helper
functions and uses the `setbits32` function to enforce bit locking
as applicable.

Port of commit 2eec87a553ec ("soc/intel/alderlake: Refactor
`pmc_lockdown_cfg` function")

BUG=none
TEST=Boot to OS on google/rex.

Signed-off-by: Kapil Porwal 
Change-Id: I3622748d8fecef69c60bb3fe9bfe68fc126764b7
---
M src/soc/intel/meteorlake/lockdown.c
1 file changed, 25 insertions(+), 39 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/70132/1

diff --git a/src/soc/intel/meteorlake/lockdown.c b/src/soc/intel/meteorlake/lockdown.c
index 51fbdaf..bfd8854 100644
--- a/src/soc/intel/meteorlake/lockdown.c
+++ b/src/soc/intel/meteorlake/lockdown.c
@@ -12,51 +12,17 @@
 #define PCR_PSTH_CTRLREG	0x1d00
 #define PSTH_CTRLREG_IOSFPTCGE	(1 << 2)

-static void pmc_lock_pmsync(void)
-{
-	uint8_t *pmcbase;
-	uint32_t pmsyncreg;
-
-	pmcbase = pmc_mmio_regs();
-
-	pmsyncreg = read32(pmcbase + PMSYNC_TPR_CFG);
-	pmsyncreg |= PCH2CPU_TPR_CFG_LOCK;
-	write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg);
-}
-
-static void pmc_lock_abase(void)
-{
-	uint8_t *pmcbase;
-	uint32_t reg32;
-
-	pmcbase = pmc_mmio_regs();
-
-	reg32 = read32(pmcbase + GEN_PMCON_B);
-	reg32 |= (SLP_STR_POL_LOCK | ACPI_BASE_LOCK);
-	write32(pmcbase + GEN_PMCON_B, reg32);
-}
-
-static void pmc_lock_smi(void)
-{
-	uint8_t *pmcbase;
-	uint8_t reg8;
-
-	pmcbase = pmc_mmio_regs();
-
-	reg8 = read8(pmcbase + GEN_PMCON_B);
-	reg8 |= SMI_LOCK;
-	write8(pmcbase + GEN_PMCON_B, reg8);
-}
-
 static void pmc_lockdown_cfg(int chipset_lockdown)
 {
+	uint8_t *pmcbase = pmc_mmio_regs();
+
    /* PMSYNC */
-	pmc_lock_pmsync();
+	setbits32(pmcbase + PMSYNC_TPR_CFG, PCH2CPU_TPR_CFG_LOCK);
    /* Lock down ABASE and sleep stretching policy */
-	pmc_lock_abase();
+	setbits32(pmcbase + GEN_PMCON_B, SLP_STR_POL_LOCK | ACPI_BASE_LOCK);

if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT)
-		pmc_lock_smi();
+		setbits32(pmcbase + GEN_PMCON_B, SMI_LOCK);
 }

static void soc_die_lockdown_cfg(void)