Attention is currently required from: Damien Zammit, Michał Żygowski, Piotr Król, Felix Held. Michał Kopeć has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63700 )
Change subject: superio/ite/common: Decouple TMPIN from thermal config ......................................................................
superio/ite/common: Decouple TMPIN from thermal config
Some ITE SuperIOs can read any internal or external temperature sources to any temperature reading registers. Therefore, decouple TMPINn mode config from thermal offset/range config.
Change-Id: I9650a26d79c325fd629adb24a8d897fd62e5f0a5 Signed-off-by: Michał Kopeć michal.kopec@3mdeb.com --- M src/mainboard/acer/g43t-am3/devicetree.cb M src/mainboard/foxconn/g41s-k/devicetree.cb M src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb M src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/superio/ite/common/env_ctrl.c M src/superio/ite/common/env_ctrl_chip.h 7 files changed, 46 insertions(+), 21 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/63700/1
diff --git a/src/mainboard/acer/g43t-am3/devicetree.cb b/src/mainboard/acer/g43t-am3/devicetree.cb index a713f34..f8d426d1 100644 --- a/src/mainboard/acer/g43t-am3/devicetree.cb +++ b/src/mainboard/acer/g43t-am3/devicetree.cb @@ -54,9 +54,9 @@ register "TMPIN1.mode" = "THERMAL_DIODE" register "TMPIN2.mode" = "THERMAL_RESISTOR" register "TMPIN3.mode" = "THERMAL_PECI" - register "TMPIN3.offset" = "100" - register "TMPIN3.min" = "0" - register "TMPIN3.max" = "100" + register "TEMP3.offset" = "100" + register "TEMP3.min" = "0" + register "TEMP3.max" = "100"
register "FAN1.mode" = "FAN_SMART_AUTOMATIC" # CPU fan register "FAN1.smart.tmpin" = "3" diff --git a/src/mainboard/foxconn/g41s-k/devicetree.cb b/src/mainboard/foxconn/g41s-k/devicetree.cb index 9bde4b2..d9eb149 100644 --- a/src/mainboard/foxconn/g41s-k/devicetree.cb +++ b/src/mainboard/foxconn/g41s-k/devicetree.cb @@ -53,7 +53,7 @@ device pci 1f.0 on # ISA bridge chip superio/ite/it8720f # Super I/O register "TMPIN1.mode" = "THERMAL_DIODE" - register "TMPIN1.offset" = "0" + register "TEMP1.offset" = "0" register "TMPIN2.mode" = "THERMAL_RESISTOR" register "TMPIN3.mode" = "THERMAL_MODE_DISABLED"
diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb index c0f198f..6880b85 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb @@ -102,7 +102,7 @@ register "TMPIN1.mode" = "THERMAL_RESISTOR" register "TMPIN2.mode" = "THERMAL_RESISTOR" register "TMPIN3.mode" = "THERMAL_DIODE" - register "TMPIN3.offset" = "0" + register "TEMP3.offset" = "0" register "ec.vin_mask" = "VIN_ALL"
register "FAN1.mode" = "FAN_SMART_AUTOMATIC" diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb index 6328bc6..d7ddf9e 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb @@ -72,7 +72,7 @@ register "TMPIN1.mode" = "THERMAL_RESISTOR" register "TMPIN2.mode" = "THERMAL_RESISTOR" register "TMPIN3.mode" = "THERMAL_DIODE" - register "TMPIN3.offset" = "0" + register "TEMP3.offset" = "0" register "ec.vin_mask" = "VIN7 | VIN4 | VIN3 | VIN2 | VIN1 | VIN0"
register "FAN1.mode" = "FAN_SMART_AUTOMATIC" diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index 39c2e33..d4bbbac 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -194,10 +194,10 @@ end chip superio/ite/it8786e register "TMPIN1.mode" = "THERMAL_PECI" - register "TMPIN1.offset" = "100" - register "TMPIN1.min" = "128" + register "TEMP1.offset" = "100" + register "TEMP1.min" = "128" register "TMPIN2.mode" = "THERMAL_RESISTOR" - register "TMPIN2.min" = "128" + register "TEMP2.min" = "128" register "TMPIN3.mode" = "THERMAL_MODE_DISABLED" register "ec.vin_mask" = "VIN_ALL" # FAN1 is CPU fan (on board) diff --git a/src/superio/ite/common/env_ctrl.c b/src/superio/ite/common/env_ctrl.c index 9149c58..f329935 100644 --- a/src/superio/ite/common/env_ctrl.c +++ b/src/superio/ite/common/env_ctrl.c @@ -58,7 +58,7 @@ * into TMPINx register */ static void enable_tmpin(const u16 base, const u8 tmpin, - const struct ite_ec_thermal_config *const conf) + const struct ite_ec_tmpin_config *const conf) { u8 reg; u8 reg_extra; @@ -109,19 +109,26 @@ }
pnp_write_hwm5_index(base, ITE_EC_ADC_TEMP_CHANNEL_ENABLE, reg); +} + +/* + * Configure temperature reading registers (offsets, limits) + */ +static void enable_temp(const u16 base, const u8 temp, + const struct ite_ec_thermal_config *const conf) +{ + u8 reg;
/* Set temperature offsets */ - if (conf->mode != THERMAL_RESISTOR) { - reg = pnp_read_hwm5_index(base, ITE_EC_BEEP_ENABLE); - reg |= ITE_EC_TEMP_ADJUST_WRITE_ENABLE; - pnp_write_hwm5_index(base, ITE_EC_BEEP_ENABLE, reg); - pnp_write_hwm5_index(base, ITE_EC_TEMP_ADJUST[tmpin-1], conf->offset); - } + reg = pnp_read_hwm5_index(base, ITE_EC_BEEP_ENABLE); + reg |= ITE_EC_TEMP_ADJUST_WRITE_ENABLE; + pnp_write_hwm5_index(base, ITE_EC_BEEP_ENABLE, reg); + pnp_write_hwm5_index(base, ITE_EC_TEMP_ADJUST[temp], conf->offset);
/* Set temperature limits */ u8 max = conf->max; - pnp_write_hwm5_index(base, ITE_EC_HIGH_TEMP_LIMIT(tmpin), max ? max : 127); - pnp_write_hwm5_index(base, ITE_EC_LOW_TEMP_LIMIT(tmpin), conf->min); + pnp_write_hwm5_index(base, ITE_EC_HIGH_TEMP_LIMIT(temp), max ? max : 127); + pnp_write_hwm5_index(base, ITE_EC_LOW_TEMP_LIMIT(temp), conf->min);
/* Enable the startup of monitoring operation */ reg = pnp_read_hwm5_index(base, ITE_EC_CONFIGURATION); @@ -286,6 +293,10 @@ for (i = 0; i < ITE_EC_TMPIN_CNT; ++i) enable_tmpin(base, i + 1, &conf->tmpin[i]);
+ /* Configure temperature reading registers */ + for (i = 0; i < ITE_EC_TEMP_CNT; ++i) + enable_temp(base, i, &conf->temp[i]); + /* Enable External Sensor SMBus Host if configured */ if (conf->smbus_en) { pnp_write_hwm5_index(base, ITE_EC_INTERFACE_SELECT, diff --git a/src/superio/ite/common/env_ctrl_chip.h b/src/superio/ite/common/env_ctrl_chip.h index 2bb0780..947df57 100644 --- a/src/superio/ite/common/env_ctrl_chip.h +++ b/src/superio/ite/common/env_ctrl_chip.h @@ -5,6 +5,8 @@
#define ITE_EC_TMPIN_CNT 3
+#define ITE_EC_TEMP_CNT 3 + #if CONFIG(SUPERIO_ITE_ENV_CTRL_5FANS) #define ITE_EC_FAN_CNT 5 #else @@ -12,15 +14,18 @@ #endif
/* Supported thermal mode on TMPINx */ -enum ite_ec_thermal_mode { +enum ite_ec_tmpin_mode { THERMAL_MODE_DISABLED = 0, THERMAL_DIODE, THERMAL_RESISTOR, THERMAL_PECI, };
+struct ite_ec_tmpin_config { + enum ite_ec_tmpin_mode mode; +}; + struct ite_ec_thermal_config { - enum ite_ec_thermal_mode mode; /* Offset is used for diode sensors and PECI */ u8 offset; /* Limits */ @@ -78,7 +83,12 @@ /* * Enable temperature sensors in given mode. */ - struct ite_ec_thermal_config tmpin[ITE_EC_TMPIN_CNT]; + struct ite_ec_tmpin_config tmpin[ITE_EC_TMPIN_CNT]; + + /* + * Configure temperature reading registers. + */ + struct ite_ec_thermal_config temp[ITE_EC_TEMP_CNT];
/* * Enable a FAN in given mode. @@ -105,6 +115,10 @@ #define TMPIN2 ec.tmpin[1] #define TMPIN3 ec.tmpin[2]
+#define TEMP1 ec.temp[0] +#define TEMP2 ec.temp[1] +#define TEMP3 ec.temp[2] + #define FAN1 ec.fan[0] #define FAN2 ec.fan[1] #define FAN3 ec.fan[2]