[coreboot-gerrit] Change in coreboot[master]: mb/google/brya/var/vell: update gpio override

[Kevin Chiu (Code Review)]

Attention is currently required from: Kevin Chiu.
Hello Kevin Chiu,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/59305

to review the following change.

Change subject: mb/google/brya/var/vell: update gpio override
......................................................................

mb/google/brya/var/vell: update gpio override

BUG=b:205908918
TEST=emerge-brya coreboot

Change-Id: Icc91866f7555c294af7eed9e5d1550e73d8059d0
Signed-off-by: Kevin Chiu 
---
A src/mainboard/google/brya/variants/vell/Makefile.inc
A src/mainboard/google/brya/variants/vell/gpio.c
2 files changed, 100 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/59305/1

diff --git a/src/mainboard/google/brya/variants/vell/Makefile.inc b/src/mainboard/google/brya/variants/vell/Makefile.inc
new file mode 100644
index 0000000..009117a
--- /dev/null
+++ b/src/mainboard/google/brya/variants/vell/Makefile.inc
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+bootblock-y += gpio.c
+romstage-y += gpio.c
+ramstage-y += gpio.c
\ No newline at end of file
diff --git a/src/mainboard/google/brya/variants/vell/gpio.c b/src/mainboard/google/brya/variants/vell/gpio.c
new file mode 100644
index 0000000..a4d1d54
--- /dev/null
+++ b/src/mainboard/google/brya/variants/vell/gpio.c
@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+#include <soc/gpio.h>
+
+/* Pad configuration in ramstage */
+static const struct pad_config override_gpio_table[] = {
+	/* B15  : TIME_SYNC0 ==> NC */
+	PAD_NC(GPP_B15, NONE),
+
+	/* C3 : SML0CLK ==> NC */
+	PAD_NC(GPP_C3, NONE),
+
+	/* E3  : PROC_GP0 ==> MEM_STRAP_0 */
+	PAD_CFG_GPI(GPP_E3, NONE, DEEP),
+	/* E5  : SATA_DEVSLP1 ==> MEM_CH_SEL */
+	PAD_CFG_GPI(GPP_E5, NONE, DEEP),
+	/* E7  : PROC_GP1 ==> MEM_STRAP_3 */
+	PAD_CFG_GPI(GPP_E7, NONE, DEEP),
+
+	/* S4 : SNDW2_CLK ==> NC */
+	PAD_NC(GPP_S4, NONE),
+	/* S5 : SNDW2_DATA ==> NC */
+	PAD_NC(GPP_S5, NONE),
+	/* S6 : SNDW3_CLK ==> NC */
+	PAD_NC(GPP_S6, NONE),
+	/* S7 : SNDW3_DATA ==> NC */
+	PAD_NC(GPP_S7, NONE),
+
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+	/* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
+	/* B4  : PROC_GP3 ==> SSD_PERST_L */
+	PAD_CFG_GPO(GPP_B4, 0, DEEP),
+	/* B7  : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
+	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
+	/* B8  : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */
+	PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
+	/*
+	 * D1  : ISH_GP1 ==> FP_RST_ODL
+	 * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
+	 * To ensure proper power sequencing for the FPMCU device, reset signal is driven low
+	 * early on in bootblock, followed by enabling of power. Reset signal is deasserted
+	 * later on in ramstage. Since reset signal is asserted in bootblock, it results in
+	 * FPMCU not working after a S3 resume. This is a known issue.
+	 */
+	PAD_CFG_GPO(GPP_D1, 0, DEEP),
+	/* D2  : ISH_GP2 ==> EN_FP_PWR */
+	PAD_CFG_GPO(GPP_D2, 1, DEEP),
+        /* D11 : ISH_SPI_MISO ==> USB_C0_LSX_SOC_TX */
+        PAD_CFG_NF(GPP_D11, NONE, DEEP, NF4),
+
+	/* E3  : PROC_GP0 ==> MEM_STRAP_0 */
+	PAD_CFG_GPI(GPP_E3, NONE, DEEP),
+	/* E5  : SATA_DEVSLP1 ==> MEM_CH_SEL */
+	PAD_CFG_GPI(GPP_E5, NONE, DEEP),
+	/* E7  : PROC_GP1 ==> MEM_STRAP_3 */
+	PAD_CFG_GPI(GPP_E7, NONE, DEEP),
+
+	/* E15 : RSVD_TP ==> PCH_WP_OD */
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
+	/* E16 : RSVD_TP ==> WWAN_RST_L  */
+	PAD_CFG_GPO(GPP_E16, 0, DEEP),
+	/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
+	PAD_CFG_GPI(GPP_F18, NONE, DEEP),
+	/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
+	/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+	/* B4  : PROC_GP3 ==> SSD_PERST_L */
+	PAD_CFG_GPO(GPP_B4, 0, DEEP),
+};
+
+static const struct pad_config romstage_gpio_table[] = {
+	/* B4  : PROC_GP3 ==> SSD_PERST_L */
+	PAD_CFG_GPO(GPP_B4, 1, DEEP),
+	/* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (set here for correct power sequencing) */
+	PAD_CFG_GPO(GPP_F21, 1, DEEP),
+};
+
+const struct pad_config *variant_gpio_override_table(size_t *num)
+{
+	*num = ARRAY_SIZE(override_gpio_table);
+	return override_gpio_table;
+}
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}