Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43031 )
Change subject: mb/roda/rv11: Do not overwrite pei_data ......................................................................
mb/roda/rv11: Do not overwrite pei_data
Most of the values are already set in northbridge code.
Change-Id: I5b8986fdaddbd04ee02b71dc6120d00573a5279e Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/roda/rv11/variants/rv11/early_init.c M src/mainboard/roda/rv11/variants/rw11/early_init.c 2 files changed, 56 insertions(+), 106 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/43031/1
diff --git a/src/mainboard/roda/rv11/variants/rv11/early_init.c b/src/mainboard/roda/rv11/variants/rv11/early_init.c index ada4b9f..c733d48 100644 --- a/src/mainboard/roda/rv11/variants/rv11/early_init.c +++ b/src/mainboard/roda/rv11/variants/rv11/early_init.c @@ -8,60 +8,35 @@
void mainboard_fill_pei_data(struct pei_data *const pei_data) { - const struct pei_data pei_data_template = { - .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server - .tseg_size = CONFIG_SMM_TSEG_SIZE, - .spd_addresses = { 0xA0, 0x00, 0xA4, 0x00 }, - .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, - .ec_present = 1, - .gbe_enable = 1, - .ddr3lv_support = 0, - // 0 = leave channel enabled - // 1 = disable dimm 0 on channel - // 2 = disable dimm 1 on channel - // 3 = disable dimm 0+1 on channel - .dimm_channel0_disabled = 2, - .dimm_channel1_disabled = 2, - .max_ddr3_freq = 1600, - .usb_port_config = { - /* Enabled / OC PIN / Length */ - { 1, 0, 0x0040 }, /* P00: 1st USB3 (OC #0) */ - { 1, 4, 0x0040 }, /* P01: 2nd USB3 (OC #4) */ - { 1, 1, 0x0080 }, /* P02: 1st Multibay USB3 (OC #1) */ - { 1, 2, 0x0080 }, /* P03: 2nd Multibay USB3 (OC #2) */ - { 1, 8, 0x0040 }, /* P04: MiniPCIe 1 USB2 (no OC) */ - { 1, 8, 0x0040 }, /* P05: MiniPCIe 2 USB2 (no OC) */ - { 1, 8, 0x0040 }, /* P06: MiniPCIe 3 USB2 (no OC) */ - { 1, 8, 0x0040 }, /* P07: GPS USB2 (no OC) */ - { 1, 8, 0x0040 }, /* P08: MiniPCIe 4 USB2 (no OC) */ - { 1, 3, 0x0040 }, /* P09: Express Card USB2 (OC #3) */ - { 1, 8, 0x0040 }, /* P10: SD card reader USB2 (no OC) */ - { 1, 8, 0x0040 }, /* P11: Sensors Hub? USB2 (no OC) */ - { 1, 8, 0x0040 }, /* P12: Touch Screen USB2 (no OC) */ - { 1, 5, 0x0040 }, /* P13: reserved? USB2 (OC #5) */ - }, - .usb3 = { - .mode = 3, /* Smart Auto? */ - .hs_port_switch_mask = 0xf, /* All four ports. */ - .preboot_support = 1, /* preOS driver? */ - .xhci_streams = 1, /* Enable. */ - }, - .pcie_init = 1, + pei_data->system_type = 0; /* 0 Mobile, 1 Desktop/Server */ + pei_data->ec_present = 1; + pei_data->spd_addresses = { 0xA0, 0x00, 0xA4, 0x00 }; + pei_data->max_ddr3_freq = 1600; + + pei_data->usb_port_config = { + /* Enabled / OC PIN / Length */ + { 1, 0, 0x0040 }, /* P00: 1st USB3 (OC #0) */ + { 1, 4, 0x0040 }, /* P01: 2nd USB3 (OC #4) */ + { 1, 1, 0x0080 }, /* P02: 1st Multibay USB3 (OC #1) */ + { 1, 2, 0x0080 }, /* P03: 2nd Multibay USB3 (OC #2) */ + { 1, 8, 0x0040 }, /* P04: MiniPCIe 1 USB2 (no OC) */ + { 1, 8, 0x0040 }, /* P05: MiniPCIe 2 USB2 (no OC) */ + { 1, 8, 0x0040 }, /* P06: MiniPCIe 3 USB2 (no OC) */ + { 1, 8, 0x0040 }, /* P07: GPS USB2 (no OC) */ + { 1, 8, 0x0040 }, /* P08: MiniPCIe 4 USB2 (no OC) */ + { 1, 3, 0x0040 }, /* P09: Express Card USB2 (OC #3) */ + { 1, 8, 0x0040 }, /* P10: SD card reader USB2 (no OC) */ + { 1, 8, 0x0040 }, /* P11: Sensors Hub? USB2 (no OC) */ + { 1, 8, 0x0040 }, /* P12: Touch Screen USB2 (no OC) */ + { 1, 5, 0x0040 }, /* P13: reserved? USB2 (OC #5) */ }; - *pei_data = pei_data_template; + + pei_data->usb3 = { + .mode = 3, /* Smart Auto? */ + .hs_port_switch_mask = 0xf, /* All four ports. */ + .preboot_support = 1, /* preOS driver? */ + .xhci_streams = 1, /* Enable. */ + }; }
const struct southbridge_usb_port mainboard_usb_ports[] = { diff --git a/src/mainboard/roda/rv11/variants/rw11/early_init.c b/src/mainboard/roda/rv11/variants/rw11/early_init.c index f56a5e4..eafd3b9 100644 --- a/src/mainboard/roda/rv11/variants/rw11/early_init.c +++ b/src/mainboard/roda/rv11/variants/rw11/early_init.c @@ -38,60 +38,35 @@
void mainboard_fill_pei_data(struct pei_data *const pei_data) { - const struct pei_data pei_data_template = { - .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server - .tseg_size = CONFIG_SMM_TSEG_SIZE, - .spd_addresses = { 0xA0, 0xA2, 0xA4, 0xA6 }, - .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, - .ec_present = 1, - .gbe_enable = 1, - .ddr3lv_support = 0, - // 0 = leave channel enabled - // 1 = disable dimm 0 on channel - // 2 = disable dimm 1 on channel - // 3 = disable dimm 0+1 on channel - .dimm_channel0_disabled = 0, - .dimm_channel1_disabled = 0, - .max_ddr3_freq = 1600, - .usb_port_config = { - /* Enabled / OC PIN / Length */ - { 1, 0, 0x0080 }, /* P00: 1st (left) USB3 (OC #0) */ - { 1, 0, 0x0080 }, /* P01: 2nd (left) USB3 (OC #0) */ - { 1, 1, 0x0080 }, /* P02: 1st Multibay USB3 (OC #1) */ - { 1, 1, 0x0080 }, /* P03: 2nd Multibay USB3 (OC #1) */ - { 1, 8, 0x0040 }, /* P04: MiniPCIe 1 USB2 (no OC) */ - { 1, 8, 0x0040 }, /* P05: MiniPCIe 2 USB2 (no OC) */ - { 1, 8, 0x0040 }, /* P06: USB Hub x4 USB2 (no OC) */ - { 1, 8, 0x0040 }, /* P07: MiniPCIe 4 USB2 (no OC) */ - { 1, 8, 0x0080 }, /* P08: SD card reader USB2 (no OC) */ - { 1, 4, 0x0080 }, /* P09: 3rd (right) USB2 (OC #4) */ - { 1, 5, 0x0040 }, /* P10: 4th (right) USB2 (OC #5) */ - { 1, 8, 0x0040 }, /* P11: 3rd Multibay USB2 (no OC) */ - { 1, 8, 0x0080 }, /* P12: misc internal USB2 (no OC) */ - { 1, 6, 0x0080 }, /* P13: misc internal USB2 (OC #6) */ - }, - .usb3 = { - .mode = 3, /* Smart Auto? */ - .hs_port_switch_mask = 0xf, /* All four ports. */ - .preboot_support = 1, /* preOS driver? */ - .xhci_streams = 1, /* Enable. */ - }, - .pcie_init = 1, + pei_data->system_type = 0; /* 0 Mobile, 1 Desktop/Server */ + pei_data->ec_present = 1; + pei_data->spd_addresses = { 0xA0, 0xA2, 0xA4, 0xA6 }; + pei_data->max_ddr3_freq = 1600; + + pei_data->usb_port_config = { + /* Enabled / OC PIN / Length */ + { 1, 0, 0x0080 }, /* P00: 1st (left) USB3 (OC #0) */ + { 1, 0, 0x0080 }, /* P01: 2nd (left) USB3 (OC #0) */ + { 1, 1, 0x0080 }, /* P02: 1st Multibay USB3 (OC #1) */ + { 1, 1, 0x0080 }, /* P03: 2nd Multibay USB3 (OC #1) */ + { 1, 8, 0x0040 }, /* P04: MiniPCIe 1 USB2 (no OC) */ + { 1, 8, 0x0040 }, /* P05: MiniPCIe 2 USB2 (no OC) */ + { 1, 8, 0x0040 }, /* P06: USB Hub x4 USB2 (no OC) */ + { 1, 8, 0x0040 }, /* P07: MiniPCIe 4 USB2 (no OC) */ + { 1, 8, 0x0080 }, /* P08: SD card reader USB2 (no OC) */ + { 1, 4, 0x0080 }, /* P09: 3rd (right) USB2 (OC #4) */ + { 1, 5, 0x0040 }, /* P10: 4th (right) USB2 (OC #5) */ + { 1, 8, 0x0040 }, /* P11: 3rd Multibay USB2 (no OC) */ + { 1, 8, 0x0080 }, /* P12: misc internal USB2 (no OC) */ + { 1, 6, 0x0080 }, /* P13: misc internal USB2 (OC #6) */ }; - *pei_data = pei_data_template; + + pei_data->usb3 = { + .mode = 3, /* Smart Auto? */ + .hs_port_switch_mask = 0xf, /* All four ports. */ + .preboot_support = 1, /* preOS driver? */ + .xhci_streams = 1, /* Enable. */ + }; }
const struct southbridge_usb_port mainboard_usb_ports[] = {