[coreboot-gerrit] Change in coreboot[master]: security/intel/txt: Improve MTRR setup for GETSEC[ENTERACCS]

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44880 )

Change subject: security/intel/txt: Improve MTRR setup for GETSEC[ENTERACCS]
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Patch Set 9:

(1 comment)

https://review.coreboot.org/c/coreboot/+/44880/2/src/security/intel/txt/gets... 
File src/security/intel/txt/getsec_enteraccs.S:

https://review.coreboot.org/c/coreboot/+/44880/2/src/security/intel/txt/gets... 
PS2, Line 184: 	movd	%eax, %xmm0			/* XMM0: Base address of next MTRR */
> We're already using SSE registers in the code below. […]

Ack