Meera Ravindranath has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48416 )
Change subject: mb/intel/adlrvp_p: Support VBT for LP4, LP5 and DDR5 SKUs ......................................................................
mb/intel/adlrvp_p: Support VBT for LP4, LP5 and DDR5 SKUs
Add support to pick the right vbt from cbfs according to SKU ID.
Change-Id: I8795cc67d87429eddb31328f1e2a90c346b53533 Signed-off-by: Meera Ravindranath meera.ravindranath@intel.com --- M src/mainboard/intel/adlrvp/Makefile.inc M src/mainboard/intel/adlrvp/mainboard.c 2 files changed, 17 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/48416/1
diff --git a/src/mainboard/intel/adlrvp/Makefile.inc b/src/mainboard/intel/adlrvp/Makefile.inc index de92406..036b23c 100644 --- a/src/mainboard/intel/adlrvp/Makefile.inc +++ b/src/mainboard/intel/adlrvp/Makefile.inc @@ -21,6 +21,11 @@ ramstage-y += board_id.c ramstage-y += gpio.c
+cbfs-files-y += vbt_lp4.bin +vbt_lp4.bin-file := 3rdparty/blobs/mainboard/intel/adlrvp_p/vbt_lp4.bin +vbt_lp4.bin-type := raw +vbt_lp4.bin-compression := lzma + CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/intel/adlrvp/mainboard.c b/src/mainboard/intel/adlrvp/mainboard.c index fb25578..35385e3 100644 --- a/src/mainboard/intel/adlrvp/mainboard.c +++ b/src/mainboard/intel/adlrvp/mainboard.c @@ -3,6 +3,7 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> #include <device/device.h> +#include <drivers/intel/gma/opregion.h> #include <ec/ec.h> #include <soc/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> @@ -38,3 +39,14 @@ .init = mainboard_init, .enable_dev = mainboard_enable, }; + +const char *mainboard_vbt_filename(void) +{ + uint8_t sku_id = get_board_id(); + if (sku_id == 0x10) { + return "vbt_lp4.bin"; + } + else { + return "vbt.bin"; + } +}