Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... File src/soc/intel/alderlake/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 309:
We have also seen some cases in past platform where FSP unnecessary program new GPIO in Native mode (this is only what FSP can do)
Sorry, the latter part again is untrue. I was and I am able to change them in coreboot, just like the "normal" GPIOs. I've been experimenting with those "special" GPIOs a few days on CML.
i have confirmed from EDS owner that those GPIOs are not intended to program by BIOS
FSP indirectly claims being part of "BIOS" in multiple comments in the source. You see comments like "BIOS is expected to do xyz", at code locations doing exactly what's in the comments. Yes, that may be a weak conclusion. However, the point is it does program these GPIOs.
Yes, FSP can only set GPIO to NF but my point is if board design don't like to use that GPIO in NF then FSP shouldn't do that override even, hence we have guarded all NF inside FSP using possible UPD to avoid overrides
Yes, this is right and I fully agree. There are UPDs that make FSP configure those pads as NF1. For a (probably incomplete) list for CNL, see CB:45211.