Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34995 )
Change subject: arch/x86: Cache the TSEG region at the top of ram ......................................................................
Patch Set 8:
(2 comments)
https://review.coreboot.org/c/coreboot/+/34995/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34995/3//COMMIT_MSG@7 PS3, Line 7: arch/x86: Add postcar_frame_setup_top_of_dram_usage() API
intel/cannonlake: Cache the TSEG region […]
Done
https://review.coreboot.org/c/coreboot/+/34995/3/src/arch/x86/postcar_loader... File src/arch/x86/postcar_loader.c:
https://review.coreboot.org/c/coreboot/+/34995/3/src/arch/x86/postcar_loader... PS3, Line 153: MTRR_TYPE_WRBACK);
Remember what I wrote earlier about postcar_frame_setup_top_of_dram_usage() setting new requiremen […]
Ack