[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Switch to CSE Lite RW at BS_DEV_INIT_CHIPS entry

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42790 )

Change subject: soc/intel/tigerlake: Switch to CSE Lite RW at BS_DEV_INIT_CHIPS entry
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soc/intel/tigerlake: Switch to CSE Lite RW at BS_DEV_INIT_CHIPS entry

This is a W/A to avoid a communication issue with CSE Lite over Heci
interface. This will help to avoid boot failures with CSE Lite until
the permanent fix is available.

BUG=b:159884143
TEST=build and boot volteer with serial and non-serial image

Change-Id: Ib136a2154b36c63c7147bbcfbf1ca7beac3a5685
Signed-off-by: Jamie Ryu 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42790
Reviewed-by: Nick Vaccaro 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/common/block/cse/cse_lite.c
1 file changed, 4 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nick Vaccaro: Looks good to me, approved
  Jamie Ryu: Looks good to me, but someone else must approve

diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c
index 3077c7f..8e43e35 100644
--- a/src/soc/intel/common/block/cse/cse_lite.c
+++ b/src/soc/intel/common/block/cse/cse_lite.c
@@ -361,4 +361,8 @@
    }
 }

+#if CONFIG(SOC_INTEL_TIGERLAKE)
+BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_ENTRY, cse_fw_sync, NULL);
+#else
 BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, cse_fw_sync, NULL);
+#endif