[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Update PCH and CPU PCIe RP table

[Furquan Shaikh (Code Review)]

Attention is currently required from: Nico Huber, Subrata Banik, Michael Niewöhner, EricR Lai.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49021 )

Change subject: soc/intel/alderlake: Update PCH and CPU PCIe RP table
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Patch Set 8:

(2 comments)

File src/soc/intel/alderlake/pcie_rp.c:

https://review.coreboot.org/c/coreboot/+/49021/comment/b84c252a_c5da20f7 
PS8, Line 18: static const struct pcie_rp_group cpu_rp_groups[] = {
Can you please add a comment here indicating that this order is basically aligned with FSP expectations for the CPU PCIe UPD?

https://review.coreboot.org/c/coreboot/+/49021/comment/d998634a_5b42e478 
PS8, Line 21: 	{ .slot = SA_DEV_SLOT_CPU_6, .start = 2, .count = 1 },
This table needs to end with { 0 }.