[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Do initial SoC commit

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36087 )

Change subject: soc/intel/tigerlake: Do initial SoC commit
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Patch Set 10:
> Patch Set 10:
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> (17 comments)
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> I appreciate the effort to fix some issues in other intel/soc targets before moving forward with TGL. It might be a bit easier to track changes if this commit was split up in smaller changes. e.g. split ACPI, bootblock, romstage, ramstage callbacks / PCI drivers, ... There is no mainboard target here so for buildtests it's mostly fine to have one mainboard on top of the soc CL. If one smaller change is ready it can get +2 and get merged independently from other changes. Also coreboot is a moving target so if something changes only a smaller CL needs updating on a rebase vs the big all in one change.

Also one more thought, will wait for base clean up patches to get merged by tomorrow and then we could address your further review comment here in this CL itself before splitting into 4 CL as mentioned. is that okay ?