Attention is currently required from: Tim Wawrzynczak. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62987 )
Change subject: soc/intel/alderlake: Log CSE RO write protection info for ADL ......................................................................
Patch Set 7:
(1 comment)
File src/soc/intel/alderlake/me.c:
https://review.coreboot.org/c/coreboot/+/62987/comment/43236357_26779a09 PS7, Line 111: die
Sorry I mean this, here, is it really worth halting boot here because of this?
We will see the issue (mfg mode disabled but WP for CSE RO is not enabled) in the factory itself.
If all goes well at factory, we will not see the buggy configuration in the shipping systems. Since, GPR0 protection can't be edited in the shipping system as this information is part of Descriptor Region.
Adding the condition, it get caught in the factory itself. We can remove the halt, but we should have a factory test case ( or FAFT Test) that should report failure when the test is run. I check internally to extend EOM FAFT test case to cover CSE RO WP status. WDYT?