[coreboot-gerrit] [S] Change in coreboot[master]: mb/google/rex/var/screebo: enable fingerprint

[Jakub Czapiga (Code Review)]

Jakub Czapiga has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75287 )

Change subject: mb/google/rex/var/screebo: enable fingerprint
......................................................................

mb/google/rex/var/screebo: enable fingerprint

BUG=b:278156430
TEST=verify the fingerprint on screebo

Change-Id: I986e470b28145f7b17427e794055929a4283c721
Signed-off-by: Simon Zhou 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75287
Reviewed-by: Subrata Banik 
Tested-by: build bot (Jenkins) 
Reviewed-by: Dolan Liu 
Reviewed-by: Kapil Porwal 
---
M src/mainboard/google/rex/variants/screebo/gpio.c
M src/mainboard/google/rex/variants/screebo/overridetree.cb
2 files changed, 34 insertions(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Subrata Banik: Looks good to me, approved
  Kapil Porwal: Looks good to me, approved
  Dolan Liu: Looks good to me, but someone else must approve

diff --git a/src/mainboard/google/rex/variants/screebo/gpio.c b/src/mainboard/google/rex/variants/screebo/gpio.c
index 7f5f72f..f31506c 100644
--- a/src/mainboard/google/rex/variants/screebo/gpio.c
+++ b/src/mainboard/google/rex/variants/screebo/gpio.c
@@ -398,7 +398,7 @@
    PAD_CFG_GPO(GPP_B08, 0, DEEP),
    /* A20 : [] ==> SSD_PERST_L */
    PAD_CFG_GPO(GPP_A20, 0, DEEP),
-	/* GPP_C23 : [] ==> FP_RST_ODL */
+	/* GPP_C21 : [] ==> FP_RST_ODL */
    PAD_CFG_GPO(GPP_C21, 0, DEEP),
    /* GPP_D02 : [] ==> SD_PERST_L */
    PAD_CFG_GPO(GPP_D02, 1, DEEP),
diff --git a/src/mainboard/google/rex/variants/screebo/overridetree.cb b/src/mainboard/google/rex/variants/screebo/overridetree.cb
index 9e3f9f6..2e7b208 100644
--- a/src/mainboard/google/rex/variants/screebo/overridetree.cb
+++ b/src/mainboard/google/rex/variants/screebo/overridetree.cb
@@ -319,6 +319,21 @@
    			device i2c 50 on end
    		end
    	end
+		device ref gspi1 on
+			chip drivers/spi/acpi
+				register "name" = ""CRFP""
+				register "hid" = "ACPI_DT_NAMESPACE_HID"
+				register "uid" = "1"
+				register "compat_string" = ""google,cros-ec-spi""
+				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E10_IRQ)"
+				register "wake" = "GPE0_DW1_10"
+				register "has_power_resource" = "1"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C21)"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B08)"
+				register "enable_delay_ms" = "3"
+				device spi 0 on end
+			end # FPMCU
+		end
    	device ref soc_espi on
    		chip ec/google/chromeec
    			use conn0 as mux_conn[0]