[coreboot-gerrit] Change in ...coreboot[master]: sb/intel/fsp_rangeley: Remove variable set but not used

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32942 )

Change subject: sb/intel/fsp_rangeley: Remove variable set but not used
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sb/intel/fsp_rangeley: Remove variable set but not used

Change-Id: Ia2bc9bb0f0ece5ae3a57662b54f3e7e78ce00b19
Signed-off-by: Elyes HAOUAS 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32942
Tested-by: build bot (Jenkins) 
Reviewed-by: Angel Pons 
Reviewed-by: Kyösti Mälkki 
---
M src/southbridge/intel/fsp_rangeley/romstage.c
1 file changed, 1 insertion(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Kyösti Mälkki: Looks good to me, approved
  Angel Pons: Looks good to me, but someone else must approve

diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c
index 19e470e..2c2427e 100644
--- a/src/southbridge/intel/fsp_rangeley/romstage.c
+++ b/src/southbridge/intel/fsp_rangeley/romstage.c
@@ -90,7 +90,6 @@
  * Memory is setup and the stack is set by the FSP.
  */
 void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) {
-	int cbmem_was_initted;
    void *cbmem_hob_ptr;

timestamp_add_now(TS_AFTER_INITRAM);
@@ -113,7 +112,7 @@
    /* Decode E0000 and F0000 segment to DRAM */
    sideband_write(B_UNIT, BMISC, sideband_read(B_UNIT, BMISC) | (1 << 1) | (1 << 0));

-	cbmem_was_initted = !cbmem_recovery(0);
+	cbmem_recovery(0);

/* Save the HOB pointer in CBMEM to be used in ramstage*/
    cbmem_hob_ptr = cbmem_add(CBMEM_ID_HOB_POINTER, sizeof(*hob_list_ptr));