[coreboot-gerrit] [S] Change in coreboot[main]: soc/intel/alderlake: Add RMT+ support

[Gaggery Tsai (Code Review)]

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Dinesh Gehlot, Jamie Ryu, Jérémy Compostella, Kane Chen, Kapil Porwal, Krishna P Bhat D, Nick Vaccaro, Paul Menzel, Pratikkumar V Prajapati, Ravishankar Sarawadi, Ronak Kanabar, Subrata Banik, Tarun Tuli, V Sowmya, Wonkyu Kim.

Hello Anil Kumar K, Bora Guvendik, Cliff Huang, Jamie Ryu, Jérémy Compostella, Kane Chen, Kapil Porwal, Krishna P Bhat D, Nick Vaccaro, Pratikkumar V Prajapati, Ravishankar Sarawadi, Ronak Kanabar, Subrata Banik, Tarun Tuli, V Sowmya, Wonkyu Kim, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/77256?usp=email

to look at the new patch set (#17).

The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)

Change subject: soc/intel/alderlake: Add RMT+ support
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soc/intel/alderlake: Add RMT+ support

This patch adds Intel RMT+ (Rank Margin Test Plus) support.

BUG=b:293441360
TEST=1. Add -DBDAT_SUPPORT=1 to build FSP packages.
     2. Enable SOC_INTEL_RMT_PLUS flag with Brya.
     3. Flash the image on Brya and ensure BDAT ACPI table is
        available under /sys/firmware/acpi/tables/.

Change-Id: I3b07d12e7701628f791e6a0f5f1d14b2e7673bc4
Signed-off-by: Gaggery Tsai 
---
M src/soc/intel/alderlake/meminit.c
M src/soc/intel/alderlake/romstage/fsp_params.c
2 files changed, 18 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/77256/17