Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85710?usp=email )
Change subject: mb/starlabs/byte_adl: Put options in CFR cbtable ......................................................................
mb/starlabs/byte_adl: Put options in CFR cbtable
Change-Id: I11349397e41fb2c7a3f26ab172a2c4b30d24bc0a Signed-off-by: Sean Rhodes sean@starlabs.systems Reviewed-on: https://review.coreboot.org/c/coreboot/+/85710 Reviewed-by: Matt DeVillier matt.devillier@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/starlabs/byte_adl/Kconfig A src/mainboard/starlabs/byte_adl/cfr.c D src/mainboard/starlabs/byte_adl/cmos.default M src/mainboard/starlabs/byte_adl/cmos.layout 4 files changed, 216 insertions(+), 47 deletions(-)
Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved
diff --git a/src/mainboard/starlabs/byte_adl/Kconfig b/src/mainboard/starlabs/byte_adl/Kconfig index 7a28093..1bd2fe0 100644 --- a/src/mainboard/starlabs/byte_adl/Kconfig +++ b/src/mainboard/starlabs/byte_adl/Kconfig @@ -1,9 +1,10 @@ config BOARD_STARLABS_BYTE_SERIES def_bool n + select DRIVERS_EFI_VARIABLE_STORE + select DRIVERS_OPTION_CFR select EC_STARLABS_ITE select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES - select HAVE_CMOS_DEFAULT select HAVE_OPTION_TABLE select INTEL_GMA_HAVE_VBT select INTEL_LPSS_UART_FOR_CONSOLE diff --git a/src/mainboard/starlabs/byte_adl/cfr.c b/src/mainboard/starlabs/byte_adl/cfr.c new file mode 100644 index 0000000..81d74b9 --- /dev/null +++ b/src/mainboard/starlabs/byte_adl/cfr.c @@ -0,0 +1,214 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <boot/coreboot_tables.h> +#include <commonlib/coreboot_tables.h> +#include <drivers/option/cfr_frontend.h> +#include <inttypes.h> +#include <intelblocks/pcie_rp.h> +#include <string.h> +#include <types.h> +#include <variants.h> + +static const struct sm_object boot_option = SM_DECLARE_ENUM({ + .opt_name = "boot_option", + .ui_name = "Boot Option", + .ui_helptext = "Change the boot device in the event of a failed boot", + .default_value = 0, + .values = (const struct sm_enum_value[]) { + { "Fallback", 0 }, + { "Normal", 1 }, + SM_ENUM_VALUE_END }, +}); + +static const struct sm_object debug_level = SM_DECLARE_ENUM({ + .opt_name = "debug_level", + .ui_name = "Debug Level", + .ui_helptext = "Set the verbosity of the debug output.", + .default_value = 0, + .values = (const struct sm_enum_value[]) { + { "Emergency", 0 }, + { "Alert", 1 }, + { "Critical", 2 }, + { "Error", 3 }, + { "Warning", 4 }, + { "Notice", 5 }, + { "Info", 6 }, + { "Debug", 7 }, + { "Spew", 8 }, + SM_ENUM_VALUE_END }, +}); + +#if CONFIG(SOC_INTEL_TIGERLAKE) || CONFIG(SOC_INTEL_ALDERLAKE) || CONFIG(SOC_INTEL_RAPTORLAKE) +static const struct sm_object gna = SM_DECLARE_BOOL({ + .opt_name = "gna", + .ui_name = "Gaussian & Neural Accelerator", + .ui_helptext = "Enable or Disable the Gaussian & Neural Accelerator", + .default_value = false, +}); +#endif + +static const struct sm_object me_state = SM_DECLARE_ENUM({ + .opt_name = "me_state", + .ui_name = "Intel Management Engine", + .ui_helptext = "Enable or disable the Intel Management Engine", + .default_value = 1, + .values = (const struct sm_enum_value[]) { + { "Disabled", 1 }, + { "Enabled", 0 }, + SM_ENUM_VALUE_END }, +}); + +static const struct sm_object me_state_counter = SM_DECLARE_NUMBER({ + .opt_name = "me_state_counter", + .ui_name = "ME State Counter", + .flags = CFR_OPTFLAG_SUPPRESS, + .default_value = 0, +}); + +static const struct sm_object power_on_after_fail = SM_DECLARE_BOOL({ + .opt_name = "power_on_after_fail", + .ui_name = "Power on after failure", + .ui_helptext = "Automatically turn on after a power failure", + .default_value = false, +}); + +static const struct sm_object power_profile = SM_DECLARE_ENUM({ + .opt_name = "power_profile", + .ui_name = "Power Profile", + .ui_helptext = "Select whether to maximize performance, battery life or both.", + .default_value = 1, + .values = (const struct sm_enum_value[]) { + { "Power Saver", PP_POWER_SAVER }, + { "Balanced", PP_BALANCED }, + { "Performance", PP_PERFORMANCE }, + SM_ENUM_VALUE_END }, +}); + +#if CONFIG(SOC_INTEL_ALDERLAKE) +static const struct sm_object pciexp_aspm = SM_DECLARE_ENUM({ + .opt_name = "pciexp_aspm", + .ui_name = "PCI ASPM", + .ui_helptext = "Controls the Active State Power Management for PCI devices." + " Enabling this feature can reduce power consumption of" + " PCI-connected devices during idle times.", + .default_value = ASPM_L0S_L1, + .values = (const struct sm_enum_value[]) { + { "Disabled", ASPM_DISABLE }, + { "L0s", ASPM_L0S }, + { "L1", ASPM_L1 }, + { "L0sL1", ASPM_L0S_L1 }, + SM_ENUM_VALUE_END }, +}); + +static const struct sm_object pciexp_clk_pm = SM_DECLARE_BOOL({ + .opt_name = "pciexp_clk_pm", + .ui_name = "PCI Clock Power Management", + .ui_helptext = "Enables or disables power management for the PCI clock. When" + " enabled, it reduces power consumption during idle states." + " This can help lower overall energy use but may impact" + " performance in power-sensitive tasks.", + .default_value = true, +}); + +static const struct sm_object pciexp_l1ss = SM_DECLARE_ENUM({ + .opt_name = "pciexp_l1ss", + .ui_name = "PCI L1 Substates", + .ui_helptext = "Controls deeper power-saving states for PCI devices." + " Enabling this feature allows supported devices to achieve" + " lower power states at the cost of slightly increased" + " latency when exiting these states.", + .default_value = L1_SS_L1_2, + .values = (const struct sm_enum_value[]) { + { "Disabled", L1_SS_DISABLED }, + { "L1.1", L1_SS_L1_1 }, + { "L1.2", L1_SS_L1_2 }, + SM_ENUM_VALUE_END }, +}); +#endif + +static const struct sm_object reboot_counter = SM_DECLARE_NUMBER({ + .opt_name = "reboot_counter", + .ui_name = "Reboot Counter", + .flags = CFR_OPTFLAG_SUPPRESS, + .default_value = 0, +}); + +static const struct sm_object vtd = SM_DECLARE_BOOL({ + .opt_name = "vtd", + .ui_name = "VT-d", + .ui_helptext = "Enable or disable Intel VT-d (virtualization)", + .default_value = true, +}); + +static struct sm_obj_form performance = { + .ui_name = "Performance", + .obj_list = (const struct sm_object *[]) { + &power_profile, + NULL + }, +}; + +static struct sm_obj_form processor = { + .ui_name = "Processor", + .obj_list = (const struct sm_object *[]) { + &me_state, + &me_state_counter, + &vtd, + NULL + }, +}; + +static struct sm_obj_form power = { + .ui_name = "Power", + .obj_list = (const struct sm_object *[]) { + &power_on_after_fail, + NULL + }, +}; + +static struct sm_obj_form devices = { + .ui_name = "Devices", + .obj_list = (const struct sm_object *[]) { + #if CONFIG(SOC_INTEL_TIGERLAKE) || CONFIG(SOC_INTEL_ALDERLAKE) || CONFIG(SOC_INTEL_RAPTORLAKE) + &gna, + #endif + NULL + }, +}; + +static struct sm_obj_form pci = { + .ui_name = "PCI", + .obj_list = (const struct sm_object *[]) { + #if CONFIG(SOC_INTEL_ALDERLAKE) + &pciexp_clk_pm, + &pciexp_aspm, + &pciexp_l1ss, + #endif + NULL + }, +}; + +static struct sm_obj_form coreboot = { + .ui_name = "coreboot", + .obj_list = (const struct sm_object *[]) { + &boot_option, + &debug_level, + &reboot_counter, + NULL + }, +}; + +static struct sm_obj_form *sm_root[] = { + &performance, + &processor, + &power, + &devices, + &pci, + &coreboot, + NULL +}; + +void mb_cfr_setup_menu(struct lb_cfr *cfr_root) +{ + cfr_write_setup_menu(cfr_root, sm_root); +} diff --git a/src/mainboard/starlabs/byte_adl/cmos.default b/src/mainboard/starlabs/byte_adl/cmos.default deleted file mode 100644 index 619729f..0000000 --- a/src/mainboard/starlabs/byte_adl/cmos.default +++ /dev/null @@ -1,14 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -# hardcoded -boot_option=Fallback -# console -debug_level=Debug -# cpu -vtd=Enable -power_profile=Balanced -me_state=Disable -# Devices -wireless=Enable -webcam=Enable -gna=Disable diff --git a/src/mainboard/starlabs/byte_adl/cmos.layout b/src/mainboard/starlabs/byte_adl/cmos.layout index d780f6a..f78701f 100644 --- a/src/mainboard/starlabs/byte_adl/cmos.layout +++ b/src/mainboard/starlabs/byte_adl/cmos.layout @@ -12,22 +12,10 @@ 304 80 h 0 ramtop
# RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 2 boot_option 388 4 h 0 reboot_counter
-# ----------------------------------------------------------------- -# coreboot config options: console -395 4 e 3 debug_level # coreboot config options: cpu #400 8 r 0 reserved for century byte -408 1 e 1 vtd -416 2 e 5 power_profile -424 1 e 4 me_state -432 4 h 0 me_state_counter - -# coreboot config options: Devices -504 1 e 1 wireless -512 1 e 1 gna
# coreboot config options: check sums 984 16 h 0 check_sum @@ -42,26 +30,6 @@ 1 0 Disable 1 1 Enable
-2 0 Fallback -2 1 Normal - -3 0 Emergency -3 1 Alert -3 2 Critical -3 3 Error -3 4 Warning -3 5 Notice -3 6 Info -3 7 Debug -3 8 Spew - -4 0 Enable -4 1 Disable - -5 0 Power Saver -5 1 Balanced -5 2 Performance - # ----------------------------------------------------------------- checksums