[coreboot-gerrit] Change in ...coreboot[master]: mb/google/hatch/variants/baseboard: Set PCH Thermal Trip value to 75 ...

[Sumeet R Pawnikar (Code Review)]

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33147

Change subject: mb/google/hatch/variants/baseboard: Set PCH Thermal Trip value to 75 degree C
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mb/google/hatch/variants/baseboard: Set PCH Thermal Trip value to 75 degree C

PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and
DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal Shutdown
when S0ix is enabled.

BUG=133345634
BRANCH=None
TEST=Verified Thermal Device (B0: D20: F2) TSPM offset 0x1c [LTT (8:0)]
value is 0xFA on Hatch.

Change-Id: Ib20fae04080b28c6105e5a187cc5d7a55b48d709
Signed-off-by: Sumeet Pawnikar 
---
M src/mainboard/google/hatch/variants/baseboard/devicetree.cb
1 file changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/33147/1

diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
index 9d10cac..e5f4651 100644
--- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
@@ -47,6 +47,9 @@
    # Unlock GPIO pads
    register "PchUnlockGpioPads" = "1"

+	# PCH Trip Temperature in degree C
+	register "pch_trip_temp" = "75"
+
    register "PchPmSlpS3MinAssert" = "2"  # 50ms
    register "PchPmSlpS4MinAssert" = "1"  # 1s
    register "PchPmSlpSusMinAssert" = "1" # 500ms