Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69866 )
Change subject: cpu/intel/car: Define post codes ......................................................................
cpu/intel/car: Define post codes
This moves a lot of post code values, but unifies them between platforms, so that the same value means the same thing as much as possible.
The P4-netburst code was the most extensive and most different, so that dictated the majority of the values. Three were two values there that didn't match the other files, so those two values, 0x22 & 0x29 have duplicate entries in the table.
The rest of the entries are similar between platforms, though the values for many of them were moved to match the P4-netburst values.
POST_BOOTBLOCK and POST_POSTCAR values are intended to eventually become global, while POST_SOC would be specific to the Intel platforms.
Signed-off-by: Martin Roth gaumless@gmail.com Change-Id: If13e40b700a41d56bca85510d68da0ab31a235a9 --- M src/cpu/intel/car/core2/cache_as_ram.S M src/cpu/intel/car/non-evict/cache_as_ram.S M src/cpu/intel/car/non-evict/exit_car.S M src/cpu/intel/car/p3/cache_as_ram.S M src/cpu/intel/car/p4-netburst/cache_as_ram.S M src/cpu/intel/car/p4-netburst/exit_car.S A src/cpu/intel/car/post_codes.h 7 files changed, 115 insertions(+), 49 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/69866/1
diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S index f47ba5f..724fe1c 100644 --- a/src/cpu/intel/car/core2/cache_as_ram.S +++ b/src/cpu/intel/car/core2/cache_as_ram.S @@ -4,6 +4,8 @@ #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h>
+#include "../../post_codes.h" + .section .init .global bootblock_pre_c_entry
@@ -15,7 +17,7 @@ bootblock_pre_c_entry:
cache_as_ram: - post_code(0x20) + post_code(POST_BOOTBLOCK_CAR)
/* Send INIT IPI to all excluding ourself. */ movl $0x000C4500, %eax @@ -28,7 +30,7 @@ bt $12, %eax jc wait_for_sipi
- post_code(0x22) + post_code(POST_SOC_CLEAR_FIXED_MTRRS)
/* Clear/disable fixed MTRRs */ mov $fixed_mtrr_list_size, %ebx @@ -57,7 +59,7 @@ dec %ebx jnz clear_var_mtrr
- post_code(0x22) + post_code(POST_SOC_SET_DEF_MTRR_TYPE) /* Configure the default memory type to uncacheable. */ movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr @@ -82,7 +84,7 @@ movl $MTRR_PHYS_MASK(1), %ecx wrmsr
- post_code(0x23) + post_code(POST_SOC_SET_MTRR_BASE) /* Set Cache-as-RAM base address. */ movl $(MTRR_PHYS_BASE(0)), %ecx movl $_car_mtrr_start, %eax @@ -90,7 +92,7 @@ xorl %edx, %edx wrmsr
- post_code(0x24) + post_code(POST_SOC_SET_MTRR_MASK) /* Set Cache-as-RAM mask. */ movl $(MTRR_PHYS_MASK(0)), %ecx rdmsr @@ -98,7 +100,7 @@ orl $MTRR_PHYS_MASK_VALID, %eax wrmsr
- post_code(0x25) + post_code(POST_SOC_ENABLE_MTRRS)
/* Enable MTRR. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -126,7 +128,7 @@ shr $2, %ecx rep stosl
- post_code(0x26) + post_code(POST_SOC_DISABLE_CACHE) /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax orl $CR0_CacheDisable, %eax @@ -145,7 +147,7 @@ orl $MTRR_PHYS_MASK_VALID, %eax wrmsr
- post_code(0x28) + post_code(POST_SOC_ENABLE_CACHE) /* Enable cache. */ movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax @@ -179,7 +181,7 @@ #endif
before_c_entry: - post_code(0x29) + post_code(POST_BOOTBLOCK_BEFORE_C_ENTRY) call bootblock_c_entry_bist
/* Should never see this postcode */ diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index 0451bb4..7d6eea2 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -4,6 +4,8 @@ #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h>
+#include "../../post_codes.h" + #define NoEvictMod_MSR 0x2e0 #define BBL_CR_CTL3_MSR 0x11e
@@ -20,7 +22,7 @@ jmp check_mtrr /* Check if CPU properly reset */
cache_as_ram: - post_code(0x20) + post_code(POST_BOOTBLOCK_CAR)
/* Send INIT IPI to all excluding ourself. */ movl $0x000C4500, %eax @@ -33,14 +35,14 @@ bt $12, %eax jc wait_for_sipi
- post_code(0x21) + post_code(POST_SOC_SET_DEF_MTRR_TYPE) /* Clean-up MTRR_DEF_TYPE_MSR. */ movl $MTRR_DEF_TYPE_MSR, %ecx xorl %eax, %eax xorl %edx, %edx wrmsr
- post_code(0x22) + post_code(POST_SOC_CLEAR_FIXED_MTRRS) /* Clear/disable fixed MTRRs */ mov $fixed_mtrr_list_size, %ebx xor %eax, %eax @@ -86,7 +88,7 @@ movl $MTRR_PHYS_MASK(1), %ecx wrmsr
- post_code(0x23) + post_code(POST_SOC_SET_MTRR_BASE) /* Set Cache-as-RAM base address. */ movl $(MTRR_PHYS_BASE(0)), %ecx movl car_mtrr_start, %eax @@ -94,7 +96,7 @@ xorl %edx, %edx wrmsr
- post_code(0x24) + post_code(POST_SOC_SET_MTRR_MASK) /* Set Cache-as-RAM mask. */ movl $(MTRR_PHYS_MASK(0)), %ecx rdmsr @@ -115,7 +117,7 @@ orl $MTRR_PHYS_MASK_VALID, %eax wrmsr
- post_code(0x25) + post_code(POST_SOC_ENABLE_MTRRS)
/* Enable MTRR. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -186,7 +188,7 @@ orl $3, %eax wrmsr
- post_code(0x26) + post_code(POST_SOC_DISABLE_CACHE) /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax orl $CR0_CacheDisable, %eax @@ -197,7 +199,7 @@ orl $MTRR_PHYS_MASK_VALID, %eax wrmsr
- post_code(0x28) + post_code(POST_SOC_ENABLE_CACHE) /* Enable cache. */ movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax @@ -232,7 +234,7 @@ #endif
before_c_entry: - post_code(0x29) + post_code(POST_BOOTBLOCK_BEFORE_C_ENTRY) call bootblock_c_entry_bist
/* Should never see this postcode */ diff --git a/src/cpu/intel/car/non-evict/exit_car.S b/src/cpu/intel/car/non-evict/exit_car.S index 2834e76..bdcac29 100644 --- a/src/cpu/intel/car/non-evict/exit_car.S +++ b/src/cpu/intel/car/non-evict/exit_car.S @@ -4,6 +4,8 @@ #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h>
+#include "../../post_codes.h" + #define NoEvictMod_MSR 0x2e0
.code32 @@ -12,14 +14,14 @@ chipset_teardown_car: pop %esp
- post_code(0x30) + post_code(POST_POSTCAR_DISABLE_CACHE)
/* Disable cache. */ movl %cr0, %eax orl $CR0_CacheDisable, %eax movl %eax, %cr0
- post_code(0x31) + post_code(POST_POSTCAR_DISABLE_DEF_MTRR)
/* Disable MTRR. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -35,7 +37,7 @@ andl $~1, %eax wrmsr
- post_code(0x32) + post_code(POST_POSTCAR_TEARDOWN_DONE)
/* Return to caller. */ jmp *%esp diff --git a/src/cpu/intel/car/p3/cache_as_ram.S b/src/cpu/intel/car/p3/cache_as_ram.S index 887bb22..f14a8f2 100644 --- a/src/cpu/intel/car/p3/cache_as_ram.S +++ b/src/cpu/intel/car/p3/cache_as_ram.S @@ -4,6 +4,8 @@ #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h>
+#include "../../post_codes.h" + .section .init .global bootblock_pre_c_entry
@@ -13,7 +15,7 @@ bootblock_pre_c_entry:
cache_as_ram: - post_code(0x20) + post_code(POST_BOOTBLOCK_CAR)
/* Clear/disable fixed MTRRs */ mov $fixed_mtrr_list_size, %ebx @@ -41,7 +43,7 @@ inc %ecx dec %ebx jnz clear_var_mtrr - post_code(0x21) + post_code(POST_SOC_SET_DEF_MTRR_TYPE)
/* Configure the default memory type to uncacheable. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -49,7 +51,7 @@ andl $(~0x00000cff), %eax wrmsr
- post_code(0x22) + post_code(POST_SOC_DETERMINE_CPU_ADDR_BITS)
/* Determine CPU_ADDR_BITS and load PHYSMASK high word to %edx. */ movl $1, %eax @@ -67,7 +69,7 @@ movl $MTRR_PHYS_MASK(1), %ecx wrmsr
- post_code(0x2a) + post_code(POST_SOC_SET_CAR_BASE)
/* Set Cache-as-RAM base address. */ movl $(MTRR_PHYS_BASE(0)), %ecx @@ -83,7 +85,7 @@ orl $MTRR_PHYS_MASK_VALID, %eax wrmsr
- post_code(0x2b) + post_code(POST_SOC_ENABLE_MTRRS)
/* Enable MTRR. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -91,7 +93,7 @@ orl $MTRR_DEF_TYPE_EN, %eax wrmsr
- post_code(0x2c) + post_code(POST_SOC_ENABLE_CACHE)
/* Enable cache (CR0.CD = 0, CR0.NW = 0). */ movl %cr0, %eax @@ -113,7 +115,7 @@ xorl %eax, %eax rep stosl
- post_code(0x2d) + post_code(POST_SOC_DISABLE_CACHE) /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax orl $CR0_CacheDisable, %eax @@ -132,7 +134,7 @@ orl $MTRR_PHYS_MASK_VALID, %eax wrmsr
- post_code(0x2e) + post_code(POST_SOC_FILL_CACHE) /* Enable cache. */ movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax @@ -155,7 +157,7 @@ pushl %eax /* tsc[31:0] */
before_c_entry: - post_code(0x29) + post_code(POST_BOOTBLOCK_BEFORE_C_ENTRY) call bootblock_c_entry_bist
/* Should never see this postcode */ diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index 9ac9e22..189e702 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -5,6 +5,8 @@ #include <cpu/x86/post_code.h> #include <cpu/x86/lapic_def.h>
+#include "../../post_codes.h" + /* Macro to access Local APIC registers at default base. */ #define LAPIC(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x)
@@ -19,7 +21,7 @@ bootblock_pre_c_entry:
cache_as_ram: - post_code(0x20) + post_code(POST_BOOTBLOCK_CAR)
movl $LAPIC_BASE_MSR, %ecx rdmsr @@ -52,7 +54,7 @@ inc %ecx dec %ebx jnz clear_var_mtrr - post_code(0x21) + post_code(POST_SOC_SET_DEF_MTRR_TYPE)
/* Configure the default memory type to uncacheable. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -60,7 +62,7 @@ andl $(~0x00000cff), %eax wrmsr
- post_code(0x22) + post_code(POST_SOC_DETERMINE_CPU_ADDR_BITS)
/* Determine CPU_ADDR_BITS and load PHYSMASK high * word to %edx. @@ -104,7 +106,7 @@
bsp_init:
- post_code(0x23) + post_code(POST_SOC_BSP_INIT)
/* Send INIT IPI to all excluding ourself. */ movl LAPIC(ICR), %edi @@ -118,7 +120,7 @@ andl $LAPIC_ICR_BUSY, %ecx jnz 1b
- post_code(0x24) + post_code(POST_SOC_COUNT_CORES)
movl $1, %eax cpuid @@ -153,7 +155,7 @@
hyper_threading_cpu:
- post_code(0x25) + post_code(POST_SOC_CPU_HYPER_THREADING)
/* Send Start IPI to all excluding ourself. */ movl LAPIC(ICR), %edi @@ -168,7 +170,7 @@ andl $LAPIC_ICR_BUSY, %ecx jnz 1b
- post_code(0x26) + post_code(POST_SOC_CPU_SIBLING_DELAY)
/* Wait for sibling CPU to start. */ 1: movl $(MTRR_PHYS_BASE(0)), %ecx @@ -184,14 +186,14 @@
ap_init: - post_code(0x27) + post_code(POST_SOC_CPU_AP_INIT)
/* Do not disable cache (so BSP can enable it). */ movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0
- post_code(0x28) + post_code(POST_SOC_SET_MTRR_BASE)
/* MTRR registers are shared between HT siblings. */ movl $(MTRR_PHYS_BASE(0)), %ecx @@ -199,7 +201,7 @@ xorl %edx, %edx wrmsr
- post_code(0x29) + post_code(POST_SOC_AP_HALT)
ap_halt: cli @@ -210,7 +212,7 @@
sipi_complete:
- post_code(0x2a) + post_code(POST_SOC_SET_CAR_BASE)
/* Set Cache-as-RAM base address. */ movl $(MTRR_PHYS_BASE(0)), %ecx @@ -226,7 +228,7 @@ orl $MTRR_PHYS_MASK_VALID, %eax wrmsr
- post_code(0x2b) + post_code(POST_SOC_ENABLE_MTRRS)
/* Enable MTRR. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -269,7 +271,7 @@ wrmsr no_msr_11e:
- post_code(0x2c) + post_code(POST_SOC_ENABLE_CACHE)
/* Cache the whole rom to fetch microcode updates */ movl $MTRR_PHYS_BASE(1), %ecx @@ -296,7 +298,7 @@ jmp update_bsp_microcode end_microcode_update: #endif - post_code(0x2d) + post_code(POST_SOC_DISABLE_CACHE) /* Disable caching to change MTRR's. */ movl %cr0, %eax orl $CR0_CacheDisable, %eax @@ -336,7 +338,7 @@ wrmsr
fill_cache: - post_code(0x2e) + post_code(POST_SOC_FILL_CACHE) /* Enable cache. */ movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax @@ -379,7 +381,7 @@ #endif
before_c_entry: - post_code(0x2f) + post_code(POST_BOOTBLOCK_BEFORE_C_ENTRY) call bootblock_c_entry_bist
/* Should never see this postcode */ diff --git a/src/cpu/intel/car/p4-netburst/exit_car.S b/src/cpu/intel/car/p4-netburst/exit_car.S index 108342f..1fffaa2 100644 --- a/src/cpu/intel/car/p4-netburst/exit_car.S +++ b/src/cpu/intel/car/p4-netburst/exit_car.S @@ -4,20 +4,22 @@ #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h>
+#include "../../post_codes.h" + .code32 .global chipset_teardown_car
chipset_teardown_car: pop %esp
- post_code(0x30) + post_code(POST_POSTCAR_DISABLE_CACHE)
/* Disable cache. */ movl %cr0, %eax orl $CR0_CacheDisable, %eax movl %eax, %cr0
- post_code(0x31) + post_code(POST_POSTCAR_DISABLE_DEF_MTRR)
/* Disable MTRR. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -25,7 +27,7 @@ andl $(~MTRR_DEF_TYPE_EN), %eax wrmsr
- post_code(0x32) + post_code(POST_POSTCAR_TEARDOWN_DONE)
/* Return to caller. */ jmp *%esp diff --git a/src/cpu/intel/car/post_codes.h b/src/cpu/intel/car/post_codes.h new file mode 100644 index 0000000..3db0aeb --- /dev/null +++ b/src/cpu/intel/car/post_codes.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef CPU_INTEL_CAR_POST_CODES_H +#define CPU_INTEL_CAR_POST_CODES_H + +#define POST_BOOTBLOCK_CAR 0x20 +#define POST_SOC_SET_DEF_MTRR_TYPE 0x21 +#define POST_SOC_CLEAR_FIXED_MTRRS 0x22 // Intentional Duplicate +#define POST_SOC_DETERMINE_CPU_ADDR_BITS 0x22 +#define POST_SOC_BSP_INIT 0x23 +#define POST_SOC_COUNT_CORES 0x24 +#define POST_SOC_CPU_HYPER_THREADING 0x25 +#define POST_SOC_CPU_SIBLING_DELAY 0x26 +#define POST_SOC_CPU_AP_INIT 0x27 +#define POST_SOC_SET_MTRR_BASE 0x28 +#define POST_SOC_SET_MTRR_MASK 0x29 // Intentional Duplicate +#define POST_SOC_AP_HALT 0x29 +#define POST_SOC_SET_CAR_BASE 0x2a +#define POST_SOC_ENABLE_MTRRS 0x2b +#define POST_SOC_ENABLE_CACHE 0x2c +#define POST_SOC_DISABLE_CACHE 0x2d +#define POST_SOC_FILL_CACHE 0x2e +#define POST_BOOTBLOCK_BEFORE_C_ENTRY 0x2f + +#define POST_POSTCAR_DISABLE_CACHE 0x30 +#define POST_POSTCAR_DISABLE_DEF_MTRR 0x31 +#define POST_POSTCAR_TEARDOWN_DONE 0x32 + +#endif