[coreboot-gerrit] [S] Change in coreboot[main]: arch/riscv: Factor out common romstage code

[Maximilian Brune (Code Review)]

Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83098?usp=email )

Change subject: arch/riscv: Factor out common romstage code
......................................................................

arch/riscv: Factor out common romstage code

Adopt a similar style like we use on aarch64 and factor out the entry
functions for romstage (with and without SEPARATE_ROMSTAGE).

Signed-off-by: Maximilian Brune 
Change-Id: Ieb11d2644bf42dacf89ef15b2ec51286fe729d64
---
M src/arch/riscv/Makefile.mk
A src/arch/riscv/include/arch/stages.h
R src/arch/riscv/romstage.c
M src/mainboard/emulation/qemu-riscv/Makefile.mk
M src/mainboard/sifive/hifive-unleashed/romstage.c
M src/mainboard/sifive/hifive-unmatched/romstage.c
6 files changed, 30 insertions(+), 17 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/83098/1

diff --git a/src/arch/riscv/Makefile.mk b/src/arch/riscv/Makefile.mk
index d5defea..1e94b31 100644
--- a/src/arch/riscv/Makefile.mk
+++ b/src/arch/riscv/Makefile.mk
@@ -96,6 +96,7 @@
 ifeq ($(CONFIG_ARCH_ROMSTAGE_RISCV),y)

romstage-$(CONFIG_SEPARATE_ROMSTAGE) += romstage.S
+romstage-y += romstage.c
 romstage-y += ramdetect.c

# Build the romstage
diff --git a/src/arch/riscv/include/arch/stages.h b/src/arch/riscv/include/arch/stages.h
new file mode 100644
index 0000000..a2036ee
--- /dev/null
+++ b/src/arch/riscv/include/arch/stages.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __ARCH_STAGES_H
+#define __ARCH_STAGES_H
+
+/* This function is the romstage platform entry point, and should contain all
+   chipset and mainboard setup until DRAM is initialized and accessible. */
+void platform_romstage_main(void);
+
+#endif
diff --git a/src/mainboard/emulation/qemu-riscv/romstage.c b/src/arch/riscv/romstage.c
similarity index 63%
rename from src/mainboard/emulation/qemu-riscv/romstage.c
rename to src/arch/riscv/romstage.c
index 39df9ad..bbe7ee1 100644
--- a/src/mainboard/emulation/qemu-riscv/romstage.c
+++ b/src/arch/riscv/romstage.c
@@ -1,22 +1,29 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

+#include <arch/stages.h>
 #include <cbmem.h>
 #include <console/console.h>
 #include <program_loading.h>
 #include <romstage_common.h>
+#include <timestamp.h>
+
+__weak void platform_romstage_main(void) { /* no-op, for bring-up */ }
+
+#if CONFIG(SEPARATE_ROMSTAGE)
+void main(void)
+{
+	timestamp_add_now(TS_ROMSTAGE_START);
+
+	console_init();
+
+	romstage_main();
+}
+#endif

void __noreturn romstage_main(void)
 {
+	platform_romstage_main();
    cbmem_initialize_empty();
+
    run_ramstage();
 }
-
-#if CONFIG(SEPARATE_ROMSTAGE)
-
-void main(void)
-{
-	console_init();
-	romstage_main();
-}
-
-#endif
diff --git a/src/mainboard/emulation/qemu-riscv/Makefile.mk b/src/mainboard/emulation/qemu-riscv/Makefile.mk
index bed0f80..0699c7e4 100644
--- a/src/mainboard/emulation/qemu-riscv/Makefile.mk
+++ b/src/mainboard/emulation/qemu-riscv/Makefile.mk
@@ -6,7 +6,6 @@
 bootblock-y += clint.c

romstage-y += cbmem.c
-romstage-y += romstage.c
 romstage-y += uart.c
 romstage-y += rom_media.c
 romstage-y += clint.c
diff --git a/src/mainboard/sifive/hifive-unleashed/romstage.c b/src/mainboard/sifive/hifive-unleashed/romstage.c
index d3ecd2a..b5f214f 100644
--- a/src/mainboard/sifive/hifive-unleashed/romstage.c
+++ b/src/mainboard/sifive/hifive-unleashed/romstage.c
@@ -8,12 +8,8 @@
 #include <soc/clock.h>
 #include <soc/sdram.h>

-void main(void)
+void __noreturn platform_romstage_main(void)
 {
-	console_init();
-
-	/* TODO: Follow Section 6.3 (FSBL) of the FU540 manual */
-
    clock_init();

// re-initialize UART
diff --git a/src/mainboard/sifive/hifive-unmatched/romstage.c b/src/mainboard/sifive/hifive-unmatched/romstage.c
index a6a1c13..930e91f 100644
--- a/src/mainboard/sifive/hifive-unmatched/romstage.c
+++ b/src/mainboard/sifive/hifive-unmatched/romstage.c
@@ -9,7 +9,7 @@
 #include <soc/clock.h>
 #include <soc/sdram.h>

-void __noreturn romstage_main(void)
+void __noreturn platform_romstage_main(void)
 {
    write_csr(0x7c1, 0); // CSR_U74_FEATURE_DISABLE (enable all Features)