[coreboot-gerrit] [XS] Change in coreboot[main]: mb/erying/tgl: Drop specifying which timers to use

[Angel Pons (Code Review)]

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86093?usp=email )

(

5 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
 )Change subject: mb/erying/tgl: Drop specifying which timers to use
......................................................................

mb/erying/tgl: Drop specifying which timers to use

With 8254 timer enabled, system would hang while entering s0ix state.
If we build coreboot with both timers =N, system enters s0ix state
(although it doesn't cut the power to the platform) and can be woken
up by pressing the key on the keyboard.

Since there's less potential for data loss in case of accidental
suspend, I think it makes sense to do it this way.

Change-Id: If6e0ac1d289447c292a49111251d321c951078e2
Signed-off-by: Alicja Michalska 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86093
Reviewed-by: Angel Pons 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/erying/tgl/Kconfig
1 file changed, 0 insertions(+), 6 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, approved

diff --git a/src/mainboard/erying/tgl/Kconfig b/src/mainboard/erying/tgl/Kconfig
index 01e5dd98..e8a2a1f 100644
--- a/src/mainboard/erying/tgl/Kconfig
+++ b/src/mainboard/erying/tgl/Kconfig
@@ -30,12 +30,6 @@
 config CBFS_SIZE
    default 0xA00000

-config USE_PM_ACPI_TIMER
-	default n
-
-config USE_LEGACY_8254_TIMER
-	default y
-
 config PCIEXP_ASPM
    default n