[coreboot-gerrit] Change in coreboot[master]: util/spd_tools: Add MT53E1G32D2NP-046 WT:B LPDDR4 config

[Martin Roth (Code Review)]

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52586 )

Change subject: util/spd_tools: Add MT53E1G32D2NP-046 WT:B LPDDR4 config
......................................................................

util/spd_tools: Add MT53E1G32D2NP-046 WT:B LPDDR4 config

The revision B version of the MT53E1G32D2NP-046 memory chip will be used
in the next guybrush build.  It has a different internal layout than the
Revision A part, with 2 ZQ lines per module instead of 1.

BUG=b:186027256
TEST=Build only

Signed-off-by: Martin Roth 
Change-Id: I066f40eb890648a9be17cfe0cee20d299000c11a
---
M util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt
1 file changed, 12 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/52586/1

diff --git a/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt b/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt
index 2cc1fa4..3e6eb8b 100644
--- a/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt
+++ b/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt
@@ -61,6 +61,18 @@
             }
         },
         {
+            "name": "MT53E1G32D2NP-046 WT:B",
+            "attribs": {
+                "densityPerChannelGb": 8,
+                "banks": 8,
+                "channelsPerDie": 2,
+                "diesPerPackage": 2,
+                "bitWidthPerChannel": 16,
+                "ranksPerChannel": 1,
+                "speedMbps": 4267
+            }
+        },
+        {
             "name": "H9HKNNNCRMBVAR-NEH",
             "attribs": {
                 "densityPerChannelGb": 8,