Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/29337
Change subject: soc/amd/stoneyridge: Get rid of void pointer math ......................................................................
soc/amd/stoneyridge: Get rid of void pointer math
Pointer math with void pointers is illegal in many compilers, though it works with GCC because it assumes size of void to be 1. Change the pointers or add parenthesis to force a proper order that will not cause compile errors if compiled with a different compiler, and more importantly, don't have unsuspected side effects.
BUG=b:118484178 TEST=Build and boot grunt.
Change-Id: Ibfeb83893f09cb897d459856aff2a4ab2a74e6e5 Signed-off-by: Richard Spiegel richard.spiegel@silverbackltd.com --- M src/soc/amd/stoneyridge/northbridge.c M src/soc/amd/stoneyridge/southbridge.c 2 files changed, 17 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/29337/1
diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index a2ae52c..8d2e99f 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -182,20 +182,22 @@
static unsigned long acpi_fill_hest(acpi_hest_t *hest) { - void *addr, *current; + u8 *addr, *current;
/* Skip the HEST header. */ - current = (void *)(hest + 1); + current = (u8 *)(hest + 1);
addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); if (addr != NULL) - current += acpi_create_hest_error_source(hest, current, 0, - (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + current += acpi_create_hest_error_source(hest, + (acpi_hest_esd_t *)current, 0, + (u8 *)((u32)addr + 2), *(UINT16 *)addr - 2);
addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); if (addr != NULL) - current += acpi_create_hest_error_source(hest, current, 1, - (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + current += acpi_create_hest_error_source(hest, + (acpi_hest_esd_t *)current, 1, + (u8 *)((u32)addr + 2), *(UINT16 *)addr - 2);
return (unsigned long)current; } diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 326ea61..40f9cbe 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -429,27 +429,27 @@ void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm) { uintptr_t base = sb_spibase(); - write16((void *)base + SPI100_SPEED_CONFIG, + write16((u16 *)((u8 *)base + SPI100_SPEED_CONFIG), (norm << SPI_NORM_SPEED_NEW_SH) | (fast << SPI_FAST_SPEED_NEW_SH) | (alt << SPI_ALT_SPEED_NEW_SH) | (tpm << SPI_TPM_SPEED_NEW_SH)); - write16((void *)base + SPI100_ENABLE, SPI_USE_SPI100); + write16((u16 *)((u8 *)base + SPI100_ENABLE), SPI_USE_SPI100); }
void sb_disable_4dw_burst(void) { uintptr_t base = sb_spibase(); - write16((void *)base + SPI100_HOST_PREF_CONFIG, - read16((void *)base + SPI100_HOST_PREF_CONFIG) + write16((u16 *)((u8 *)base + SPI100_HOST_PREF_CONFIG), + read16((u16 *)((u8 *)base + SPI100_HOST_PREF_CONFIG)) & ~SPI_RD4DW_EN_HOST); }
void sb_read_mode(u32 mode) { uintptr_t base = sb_spibase(); - write32((void *)base + SPI_CNTRL0, - (read32((void *)base + SPI_CNTRL0) + write32((u32 *)((u8 *)base + SPI_CNTRL0), + (read32((u32 *)((u8 *)base + SPI_CNTRL0)) & ~SPI_READ_MODE_MASK) | mode); }
@@ -914,11 +914,11 @@ gnvs->aoac.espi = 1;
amdfw_rom = 0x20000 - (0x80000 << CONFIG_AMD_FWM_POSITION_INDEX); - xhci_fw = read32((void *)(amdfw_rom + XHCI_FW_SIG_OFFSET)); + xhci_fw = read32((u32 *)((u8 *)amdfw_rom + XHCI_FW_SIG_OFFSET));
- fwaddr = 2 + read16((void *)(xhci_fw + XHCI_FW_ADDR_OFFSET + fwaddr = 2 + read16((u16 *)((u8 *)xhci_fw + XHCI_FW_ADDR_OFFSET + XHCI_FW_BOOTRAM_SIZE)); - fwsize = read16((void *)(xhci_fw + XHCI_FW_SIZE_OFFSET + fwsize = read16((u16 *)((u8 *)xhci_fw + XHCI_FW_SIZE_OFFSET + XHCI_FW_BOOTRAM_SIZE)); gnvs->fw00 = 0; gnvs->fw01 = ((32 * KiB) << 16) + 0;