HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29847
Change subject: src: Remove duplicated round up function ......................................................................
src: Remove duplicated round up function
Fixes 7116ac8037 (src: Make use of 'CEIL_DIV(a, b)' macro across tree).
Change-Id: I9aabc3fbe7834834c92d6ba59ff0005986622a34 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/commonlib/include/commonlib/helpers.h M src/cpu/allwinner/a10/clock.c M src/cpu/x86/tsc/delay_tsc.c M src/northbridge/intel/gm45/raminit.c M src/northbridge/intel/nehalem/raminit.c M src/northbridge/via/vx900/raminit_ddr3.c M src/soc/nvidia/tegra124/clock.c M src/soc/samsung/exynos5250/cpu.c M src/soc/samsung/exynos5420/clock.c M src/soc/samsung/exynos5420/cpu.c 10 files changed, 25 insertions(+), 27 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/29847/1
diff --git a/src/commonlib/include/commonlib/helpers.h b/src/commonlib/include/commonlib/helpers.h index f2acedc..03f4306 100644 --- a/src/commonlib/include/commonlib/helpers.h +++ b/src/commonlib/include/commonlib/helpers.h @@ -36,7 +36,6 @@ #define MAX(a, b) ((a) > (b) ? (a) : (b)) #endif #define ABS(a) (((a) < 0) ? (-(a)) : (a)) -#define CEIL_DIV(a, b) (((a) + (b) - 1) / (b)) #define IS_POWER_OF_2(x) (((x) & ((x) - 1)) == 0) #define DIV_ROUND_UP(x, y) (((x) + (y) - 1) / (y)) /* diff --git a/src/cpu/allwinner/a10/clock.c b/src/cpu/allwinner/a10/clock.c index ae50e06..7ea5424 100644 --- a/src/cpu/allwinner/a10/clock.c +++ b/src/cpu/allwinner/a10/clock.c @@ -247,8 +247,8 @@ * will always be in spec, as long as AHB is in spec, although the max * AHB0 clock we can get is 125 MHz */ - axi = CEIL_DIV(actual_mhz, 450); /* Max 450 MHz */ - ahb = CEIL_DIV(actual_mhz/axi, 250); /* Max 250 MHz */ + axi = DIV_ROUND_UP(actual_mhz, 450); /* Max 450 MHz */ + ahb = DIV_ROUND_UP(actual_mhz/axi, 250); /* Max 250 MHz */ apb0 = 2; /* Max 150 MHz */
ahb_exp = log2_ceil(ahb); diff --git a/src/cpu/x86/tsc/delay_tsc.c b/src/cpu/x86/tsc/delay_tsc.c index 04f709f..a589cdb 100644 --- a/src/cpu/x86/tsc/delay_tsc.c +++ b/src/cpu/x86/tsc/delay_tsc.c @@ -83,7 +83,7 @@ if (end.lo <= CALIBRATE_DIVISOR) goto bad_ctc;
- return CEIL_DIV(end.lo, CALIBRATE_DIVISOR); + return DIV_ROUND_UP(end.lo, CALIBRATE_DIVISOR); }
/* diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index d067dc2..ddf705f 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -361,8 +361,7 @@ } }
-#define ROUNDUP_DIV(val, by) CEIL_DIV(val, by) -#define ROUNDUP_DIV_THIS(val, by) val = ROUNDUP_DIV(val, by) +#define ROUNDUP_DIV_THIS(val, by) (val = DIV_ROUND_UP(val, by)) static fsb_clock_t read_fsb_clock(void) { switch (MCHBAR32(CLKCFG_MCHBAR) & CLKCFG_FSBCLK_MASK) { diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index d0dfb75..54ef278 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -602,7 +602,7 @@ break; } } - min_cas_latency = CEIL_DIV(cas_latency_time, cycletime); + min_cas_latency = DIV_ROUND_UP(cas_latency_time, cycletime); cas_latency = 0; while (supported_cas_latencies) { cas_latency = find_highest_bit_set(supported_cas_latencies) + 3; @@ -3231,7 +3231,7 @@
static inline int div_roundup(int a, int b) { - return CEIL_DIV(a, b); + return DIV_ROUND_UP(a, b); }
static unsigned lcm(unsigned a, unsigned b) diff --git a/src/northbridge/via/vx900/raminit_ddr3.c b/src/northbridge/via/vx900/raminit_ddr3.c index 1d05fa7..7acab31 100644 --- a/src/northbridge/via/vx900/raminit_ddr3.c +++ b/src/northbridge/via/vx900/raminit_ddr3.c @@ -572,7 +572,7 @@ printram("Selected DRAM frequency: %u MHz\n", val32);
/* Find CAS and CWL latencies */ - val = CEIL_DIV(ctrl->tAA, ctrl->tCK); + val = DIV_ROUND_UP(ctrl->tAA, ctrl->tCK); printram("Minimum CAS latency : %uT\n", val); /* Find lowest supported CAS latency that satisfies the minimum value */ while (!((ctrl->cas_supported >> (val - 4)) & 1) @@ -591,30 +591,30 @@ pci_write_config8(MCU, 0xc0, reg8);
/* Find tRCD */ - val = CEIL_DIV(ctrl->tRCD, ctrl->tCK); + val = DIV_ROUND_UP(ctrl->tRCD, ctrl->tCK); printram("Selected tRCD : %uT\n", val); reg8 = ((val - 4) & 0x7) << 4; /* Find tRP */ - val = CEIL_DIV(ctrl->tRP, ctrl->tCK); + val = DIV_ROUND_UP(ctrl->tRP, ctrl->tCK); printram("Selected tRP : %uT\n", val); reg8 |= ((val - 4) & 0x7); pci_write_config8(MCU, 0xc1, reg8);
/* Find tRAS */ - val = CEIL_DIV(ctrl->tRAS, ctrl->tCK); + val = DIV_ROUND_UP(ctrl->tRAS, ctrl->tCK); printram("Selected tRAS : %uT\n", val); reg8 = ((val - 15) & 0x7) << 4; /* Find tWR */ - ctrl->WR = CEIL_DIV(ctrl->tWR, ctrl->tCK); + ctrl->WR = DIV_ROUND_UP(ctrl->tWR, ctrl->tCK); printram("Selected tWR : %uT\n", ctrl->WR); reg8 |= ((ctrl->WR - 4) & 0x7); pci_write_config8(MCU, 0xc2, reg8);
/* Find tFAW */ - tFAW = CEIL_DIV(ctrl->tFAW, ctrl->tCK); + tFAW = DIV_ROUND_UP(ctrl->tFAW, ctrl->tCK); printram("Selected tFAW : %uT\n", tFAW); /* Find tRRD */ - tRRD = CEIL_DIV(ctrl->tRRD, ctrl->tCK); + tRRD = DIV_ROUND_UP(ctrl->tRRD, ctrl->tCK); printram("Selected tRRD : %uT\n", tRRD); val = tFAW - 4 * tRRD; /* number of cycles above 4*tRRD */ reg8 = ((val - 0) & 0x7) << 4; @@ -622,11 +622,11 @@ pci_write_config8(MCU, 0xc3, reg8);
/* Find tRTP */ - val = CEIL_DIV(ctrl->tRTP, ctrl->tCK); + val = DIV_ROUND_UP(ctrl->tRTP, ctrl->tCK); printram("Selected tRTP : %uT\n", val); reg8 = ((val & 0x3) << 4); /* Find tWTR */ - val = CEIL_DIV(ctrl->tWTR, ctrl->tCK); + val = DIV_ROUND_UP(ctrl->tWTR, ctrl->tCK); printram("Selected tWTR : %uT\n", val); reg8 |= ((val - 2) & 0x7); pci_mod_config8(MCU, 0xc4, 0x3f, reg8); @@ -639,7 +639,7 @@ * Since we previously set RxC4[7] */ reg8 = pci_read_config8(MCU, 0xc5); - val = CEIL_DIV(ctrl->tRFC, ctrl->tCK); + val = DIV_ROUND_UP(ctrl->tRFC, ctrl->tCK); printram("Minimum tRFC : %uT\n", val); if (val < 30) { val = 0; @@ -652,7 +652,7 @@ pci_write_config8(MCU, 0xc5, reg8);
/* Where does this go??? */ - val = CEIL_DIV(ctrl->tRC, ctrl->tCK); + val = DIV_ROUND_UP(ctrl->tRC, ctrl->tCK); printram("Required tRC : %uT\n", val); }
diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c index 9173e62..b9a4cd1 100644 --- a/src/soc/nvidia/tegra124/clock.c +++ b/src/soc/nvidia/tegra124/clock.c @@ -247,17 +247,17 @@ 1 << 8); /* (rst) phy_divm */
write32(&clk_rst->utmip_pll_cfg1, - CEIL_DIV(khz, 8000) << 27 | /* pllu_enbl_cnt / 8 (1us) */ + DIV_ROUND_UP(khz, 8000) << 27 | /* pllu_enbl_cnt / 8 (1us) */ 0 << 16 | /* PLLU pwrdn */ 0 << 14 | /* pll_enable pwrdn */ 0 << 12 | /* pll_active pwrdn */ - CEIL_DIV(khz, 102) << 0); /* phy_stbl_cnt / 256 (2.5ms) */ + DIV_ROUND_UP(khz, 102) << 0); /* phy_stbl_cnt / 256 (2.5ms) */
/* TODO: TRM can't decide if actv is 5us or 10us, keep an eye on it */ write32(&clk_rst->utmip_pll_cfg2, 0 << 24 | /* SAMP_D/XDEV pwrdn */ - CEIL_DIV(khz, 3200) << 18 | /* phy_actv_cnt / 16 (5us) */ - CEIL_DIV(khz, 256) << 6 | /* pllu_stbl_cnt / 256 (1ms) */ + DIV_ROUND_UP(khz, 3200) << 18 | /* phy_actv_cnt / 16 (5us) */ + DIV_ROUND_UP(khz, 256) << 6 | /* pllu_stbl_cnt / 256 (1ms) */ 0 << 4 | /* SAMP_C/USB3 pwrdn */ 0 << 2 | /* SAMP_B/XHOST pwrdn */ 0 << 0); /* SAMP_A/USBD pwrdn */ diff --git a/src/soc/samsung/exynos5250/cpu.c b/src/soc/samsung/exynos5250/cpu.c index aed1114..4fdb8f8 100644 --- a/src/soc/samsung/exynos5250/cpu.c +++ b/src/soc/samsung/exynos5250/cpu.c @@ -112,7 +112,7 @@ u32 lcdbase = get_fb_base_kb() * KiB;
ram_resource(dev, 0, RAM_BASE_KB, RAM_SIZE_KB - FB_SIZE_KB); - mmio_resource(dev, 1, lcdbase / KiB, CEIL_DIV(fb_size, KiB)); + mmio_resource(dev, 1, lcdbase / KiB, DIV_ROUND_UP(fb_size, KiB));
exynos_displayport_init(dev, lcdbase, fb_size);
diff --git a/src/soc/samsung/exynos5420/clock.c b/src/soc/samsung/exynos5420/clock.c index 04125d9..0da3522 100644 --- a/src/soc/samsung/exynos5420/clock.c +++ b/src/soc/samsung/exynos5420/clock.c @@ -345,7 +345,7 @@ } printk(BIOS_DEBUG, "%s(%d): sdclkin: %ld\n", __func__, device_index, sdclkin);
- cclkin = CEIL_DIV(sdclkin, freq); + cclkin = DIV_ROUND_UP(sdclkin, freq); set_mmc_clk(device_index, cclkin); return 0; } diff --git a/src/soc/samsung/exynos5420/cpu.c b/src/soc/samsung/exynos5420/cpu.c index ecda54b..fa4cd06 100644 --- a/src/soc/samsung/exynos5420/cpu.c +++ b/src/soc/samsung/exynos5420/cpu.c @@ -114,7 +114,7 @@ dcache_clean_invalidate_by_mva((void *)lower, upper - lower); mmu_config_range(lower / MiB, (upper - lower) / MiB, DCACHE_OFF);
- mmio_resource(dev, 1, lcdbase/KiB, CEIL_DIV(fb_size, KiB)); + mmio_resource(dev, 1, lcdbase/KiB, DIV_ROUND_UP(fb_size, KiB)); }
static void tps65090_thru_ec_fet_disable(int index) @@ -134,7 +134,7 @@ u32 lcdbase = get_fb_base_kb() * KiB;
ram_resource(dev, 0, RAM_BASE_KB, RAM_SIZE_KB - FB_SIZE_KB); - mmio_resource(dev, 1, lcdbase / KiB, CEIL_DIV(fb_size, KiB)); + mmio_resource(dev, 1, lcdbase / KiB, DIV_ROUND_UP(fb_size, KiB));
/* * Disable LCD FETs before we do anything with the display.