[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Add chip config for SATA strength

[Edward O'Callaghan (Code Review)]

Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38432 )

Change subject: soc/intel/cannonlake: Add chip config for SATA strength
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Patch Set 1: Code-Review+1

(2 comments)

https://review.coreboot.org/c/coreboot/+/38432/1/src/soc/intel/cannonlake/ch... 
File src/soc/intel/cannonlake/chip.h:

https://review.coreboot.org/c/coreboot/+/38432/1/src/soc/intel/cannonlake/ch... 
PS1, Line 394: 8
I suggest using a #define FOO_MAX 8 here.

https://review.coreboot.org/c/coreboot/+/38432/1/src/soc/intel/cannonlake/ro... 
File src/soc/intel/cannonlake/romstage/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/38432/1/src/soc/intel/cannonlake/ro... 
PS1, Line 106: 8
and changing the bound to FOO_MAX here.