Timothy Pearson (tpearson@raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14073
-gerrit
commit fa72abf3605aa9009544cefc39adec81e07e7b13 Author: Timothy Pearson tpearson@raptorengineeringinc.com Date: Sat Mar 12 17:17:23 2016 -0600
nb/amd/mct_ddr3: Use correct initial UI setting during DRAM training
Rebasing change I3be808db5d15ceec4c36d17582756b01425df09a did not take into account the default UI setting introduced in change I6ae88c891e92b21dc0ca3c47b8f3d269f83b3204 , causing DRAM instability and occassional failure to boot.
Use the correct 1UI value for the modified function semantics.
Change-Id: I9fd24cf83e4c4083c6e467d49021c98e5f5f2c53 Signed-off-by: Timothy Pearson tpearson@raptorengineeringinc.com --- src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index 182fab0..15b5ea4 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -1703,7 +1703,7 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat,
/* Reset the read data timing registers to 1UI before calculating MaxRdLatency */ for (internal_lane = 0; internal_lane < MAX_BYTE_LANES; internal_lane++) - current_read_dqs_delay[internal_lane] = 0x20 << 1; + current_read_dqs_delay[internal_lane] = 0x20; write_dqs_read_data_timing_registers(current_read_dqs_delay, dev, dct, dimm, index_reg);
/* Calculate and program MaxRdLatency */