[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/block: [WIP]Add Intel common FAST_SPI code

[Barnali Sarkar (Code Review)]

Hello build bot (Jenkins), Pratikkumar Prajapati,

I'd like you to reexamine a change.  Please visit

https://review.coreboot.org/18557

to look at the new patch set (#17).

Change subject: soc/intel/common/block: [WIP]Add Intel common FAST_SPI code
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soc/intel/common/block: [WIP]Add Intel common FAST_SPI code

Create Intel Common FAST_SPI Controller code.
This code currently only contains the code for SPI initialization
required in Bootblock phase, which has the following programming -
* Get BIOS Rom Region Size
* Enable SPIBAR
* Disable the BIOS write protect so write commands are allowed
* Enable SPI Prefetching and Caching.
* SPI Controller register offsets in the common header fast_spi.h
More code will get added up in the subsequent phases.

Change-Id: I046e3b30c8efb172851dd17f49565c9ec4cb38cb
Signed-off-by: Barnali Sarkar 
---
A src/soc/intel/common/block/fast_spi/Kconfig
A src/soc/intel/common/block/fast_spi/Makefile.inc
A src/soc/intel/common/block/fast_spi/fast_spi.c
A src/soc/intel/common/block/include/intelblocks/fast_spi.h
A src/soc/intel/common/block/include/intelblocks/fast_spi_def.h
5 files changed, 369 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/18557/17