[coreboot-gerrit] Change in coreboot[master]: mb/intel/tglrvp: Enable TPM

[Anil Kumar K (Code Review)]

Anil Kumar K has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44698 )

Change subject: mb/intel/tglrvp: Enable TPM
......................................................................

mb/intel/tglrvp: Enable TPM

Bug=none
Test=emerge build successful on tglrvpwq

Signed-off-by: Anil Kumar 
Change-Id: I4a3aec98f72524e8e2a1834878ef75b9f933ae3e
---
M src/drivers/spi/tpm/tpm.c
M src/mainboard/intel/tglrvp/Kconfig
2 files changed, 9 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/44698/1

diff --git a/src/drivers/spi/tpm/tpm.c b/src/drivers/spi/tpm/tpm.c
index 4263dce..bc9f06e 100644
--- a/src/drivers/spi/tpm/tpm.c
+++ b/src/drivers/spi/tpm/tpm.c
@@ -157,6 +157,8 @@
    for (i = 0; i < 3; i++)
    	header.body[i + 1] = (addr >> (8 * (2 - i))) & 0xff;

+	udelay(100);
+
    /* CS assert wakes up the slave. */
    spi_claim_bus(&spi_slave);

diff --git a/src/mainboard/intel/tglrvp/Kconfig b/src/mainboard/intel/tglrvp/Kconfig
index eeeecc1..e4c29f8 100644
--- a/src/mainboard/intel/tglrvp/Kconfig
+++ b/src/mainboard/intel/tglrvp/Kconfig
@@ -18,6 +18,9 @@
    select DRIVERS_INTEL_ISH
    select EC_ACPI
    select PCIEXP_HOTPLUG
+	select MAINBOARD_HAS_TPM2
+	select MAINBOARD_HAS_SPI_TPM_CR50
+	select SPI_TPM

config CHROMEOS
    bool
@@ -100,9 +103,12 @@

config VBOOT
    select VBOOT_LID_SWITCH
-	select VBOOT_MOCK_SECDATA

config UART_FOR_CONSOLE
    int
    default 2
+
+config DRIVER_TPM_SPI_BUS
+        default 0x2
+
 endif