[coreboot-gerrit] Change in coreboot[master]: soc/mediatek/mt8192: Do dramc txoe training

[CK HU (Code Review)]

Hello Duan huayang,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/44722

to review the following change.

Change subject: soc/mediatek/mt8192: Do dramc txoe training
......................................................................

soc/mediatek/mt8192: Do dramc txoe training

Signed-off-by: Huayang Duan 
Change-Id: I72ae272d145f3b4aaa1076f1fec3b8b1384d4293
---
M src/soc/mediatek/mt8192/dramc_pi_calibration_api.c
M src/soc/mediatek/mt8192/dramc_pi_main.c
2 files changed, 31 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/44722/1

diff --git a/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c
index 9ccedf1..ce03db4 100644
--- a/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c
+++ b/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c
@@ -2744,6 +2744,35 @@
    }
 }

+void dramc_tx_oe_calibration(const struct ddr_cali* cali)
+{
+	u8 chn = cali->chn;
+	u8 rank = cali->rank;
+	const struct sdram_params *params = cali->params;
+	u8 large[DQS_NUMBER], small[DQS_NUMBER];
+
+	if (cali->freq_group < DDRFREQ_1600)
+		return;
+
+	for (u8 byte = 0; byte < DQS_NUMBER; byte++) {
+		large[byte] = params->tx_oe_dq_mck[chn][rank][byte];
+		small[byte] = params->tx_oe_dq_ui[chn][rank][byte];
+	}
+
+	SET32_BITFIELDS(&ch[chn].ao.shu_rk[rank].shurk_selph_dq0,
+		SHURK_SELPH_DQ0_TXDLY_OEN_DQ0, large[0],
+		SHURK_SELPH_DQ0_TXDLY_OEN_DQ1, large[1]);
+	SET32_BITFIELDS(&ch[chn].ao.shu_rk[rank].shurk_selph_dq1,
+		SHURK_SELPH_DQ1_TXDLY_OEN_DQM0, large[0],
+		SHURK_SELPH_DQ1_TXDLY_OEN_DQM1, large[1]);
+	SET32_BITFIELDS(&ch[chn].ao.shu_rk[rank].shurk_selph_dq2,
+		SHURK_SELPH_DQ2_DLY_OEN_DQ0, small[0],
+		SHURK_SELPH_DQ2_DLY_OEN_DQ1, small[1]);
+	SET32_BITFIELDS(&ch[chn].ao.shu_rk[rank].shurk_selph_dq3,
+		SHURK_SELPH_DQ3_DLY_OEN_DQM0, small[0],
+		SHURK_SELPH_DQ3_DLY_OEN_DQM1, small[1]);
+}
+
 void dramc_rx_datlat_cal(const struct ddr_cali* cali)
 {
    u8 chn = cali->chn;
diff --git a/src/soc/mediatek/mt8192/dramc_pi_main.c b/src/soc/mediatek/mt8192/dramc_pi_main.c
index 9df4285..052b320 100644
--- a/src/soc/mediatek/mt8192/dramc_pi_main.c
+++ b/src/soc/mediatek/mt8192/dramc_pi_main.c
@@ -30,7 +30,7 @@
    dramc_write_shift_mck_write_DBI(cali, tx_shift);

mr03 = (mr03 & ~(0x1 << 7)) | (dbi_state << 7);
-	dramc_mode_reg_write_by_rank(chn, rank, 3, mr03);
+	dramc_mode_reg_write_by_rank(cali, chn, rank, 3, mr03);
    mr_value->mr03[get_fsp(cali)] = mr03;

dramc_write_dbi_onoff(dbi_state);
@@ -289,6 +289,7 @@

dramc_rx_datlat_cal(cali);
    	dramc_rx_window_perbit_cal(cali, RX_WIN_TEST_ENG);
+		dramc_tx_oe_calibration(cali);
    }
    dramc_rx_dqs_gating_post_process(cali, txdly_min, txdly_max);
    dramc_dual_rank_rx_datlat_cal(cali);