Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41933 )
Change subject: southbridge/intel/wildcatpoint: Add Kconfig ......................................................................
southbridge/intel/wildcatpoint: Add Kconfig
Move the southbridge Kconfig settings to the corresponding scope.
With BUILD_TIMELESS=1 but without adding the .config file into the resulting coreboot image, google/auron (Buddy) remains identical.
Change-Id: I96424fa6b2521487a29fd624a394a21bc6e663b0 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/broadwell/Kconfig A src/southbridge/intel/wildcatpoint/Kconfig M src/southbridge/intel/wildcatpoint/Makefile.inc 3 files changed, 80 insertions(+), 75 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/41933/1
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index e61bee8..2556ee2 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -1,78 +1,6 @@ config SOC_INTEL_BROADWELL bool + select NORTHBRIDGE_INTEL_BROADWELL + select SOUTHBRIDGE_INTEL_WILDCATPOINT help Intel Broadwell and Haswell ULT support. - -if SOC_INTEL_BROADWELL - -config SOC_SPECIFIC_OPTIONS - def_bool y - select ACPI_INTEL_HARDWARE_SLEEP_VALUES - select BOOT_DEVICE_SUPPORTS_WRITES - select HAVE_POWER_STATE_AFTER_FAILURE - select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE - select HAVE_SMI_HANDLER - select HAVE_SPI_CONSOLE_SUPPORT - select HAVE_USBDEBUG - select IOAPIC - select INTEL_DESCRIPTOR_MODE_CAPABLE - select NORTHBRIDGE_INTEL_BROADWELL - select REG_SCRIPT - select RTC - select SOC_INTEL_COMMON - select SOC_INTEL_COMMON_BLOCK - select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT - select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE - select SOUTHBRIDGE_INTEL_COMMON_RESET - select SOUTHBRIDGE_INTEL_COMMON_RTC - select SOUTHBRIDGE_INTEL_COMMON_SMBUS - select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 - select SPI_FLASH - -config PCIEXP_ASPM - bool - default y - -config PCIEXP_AER - bool - default y - -config PCIEXP_COMMON_CLOCK - bool - default y - -config PCIEXP_CLK_PM - bool - default y - -config PCIEXP_L1_SUB_STATE - bool - default y - -config INTEL_PCH_UART_CONSOLE - bool "Use Serial IO UART for console" - default n - select DRIVERS_UART_8250MEM - -config INTEL_PCH_UART_CONSOLE_NUMBER - hex "Serial IO UART number to use for console" - default 0x0 - depends on INTEL_PCH_UART_CONSOLE - -config TTYS0_BASE - hex - default 0xd6000000 - depends on INTEL_PCH_UART_CONSOLE - -config EHCI_BAR - hex - default 0xd8000000 - -config SERIRQ_CONTINUOUS_MODE - bool - default y - help - If you set this option to y, the serial IRQ machine will be - operated in continuous mode. - -endif diff --git a/src/southbridge/intel/wildcatpoint/Kconfig b/src/southbridge/intel/wildcatpoint/Kconfig new file mode 100644 index 0000000..6f8c29a --- /dev/null +++ b/src/southbridge/intel/wildcatpoint/Kconfig @@ -0,0 +1,77 @@ +config SOUTHBRIDGE_INTEL_WILDCATPOINT + bool + help + Intel Wildcat Point and Lynx Point ULT PCH support. + +if SOUTHBRIDGE_INTEL_WILDCATPOINT + +config SOUTH_BRIDGE_OPTIONS + def_bool y + select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select BOOT_DEVICE_SUPPORTS_WRITES + select HAVE_POWER_STATE_AFTER_FAILURE + select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE + select HAVE_SMI_HANDLER + select HAVE_SPI_CONSOLE_SUPPORT + select HAVE_USBDEBUG + select IOAPIC + select INTEL_DESCRIPTOR_MODE_CAPABLE + select REG_SCRIPT + select RTC + select SOC_INTEL_COMMON + select SOC_INTEL_COMMON_BLOCK + select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT + select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE + select SOUTHBRIDGE_INTEL_COMMON_RESET + select SOUTHBRIDGE_INTEL_COMMON_RTC + select SOUTHBRIDGE_INTEL_COMMON_SMBUS + select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 + select SPI_FLASH + +config PCIEXP_ASPM + bool + default y + +config PCIEXP_AER + bool + default y + +config PCIEXP_COMMON_CLOCK + bool + default y + +config PCIEXP_CLK_PM + bool + default y + +config PCIEXP_L1_SUB_STATE + bool + default y + +config INTEL_PCH_UART_CONSOLE + bool "Use Serial IO UART for console" + default n + select DRIVERS_UART_8250MEM + +config INTEL_PCH_UART_CONSOLE_NUMBER + hex "Serial IO UART number to use for console" + default 0x0 + depends on INTEL_PCH_UART_CONSOLE + +config TTYS0_BASE + hex + default 0xd6000000 + depends on INTEL_PCH_UART_CONSOLE + +config EHCI_BAR + hex + default 0xd8000000 + +config SERIRQ_CONTINUOUS_MODE + bool + default y + help + If you set this option to y, the serial IRQ machine will be + operated in continuous mode. + +endif diff --git a/src/southbridge/intel/wildcatpoint/Makefile.inc b/src/southbridge/intel/wildcatpoint/Makefile.inc index f1761f2..49a2094 100644 --- a/src/southbridge/intel/wildcatpoint/Makefile.inc +++ b/src/southbridge/intel/wildcatpoint/Makefile.inc @@ -1,4 +1,4 @@ -ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y) +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_WILDCATPOINT),y)
romstage-y += early_pch.c romstage-y += early_smbus.c