[coreboot-gerrit] Change in libgfxinit[master]: [HACK] Implement WaSouthDisplayDisablePWMCGEGating: cnp

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/libgfxinit/+/46633 )

Change subject: [HACK] Implement WaSouthDisplayDisablePWMCGEGating: cnp
......................................................................

[HACK] Implement WaSouthDisplayDisablePWMCGEGating: cnp

Change-Id: I566397be4bb23c0c3bc56847414033885c51fde7
Signed-off-by: Angel Pons 
---
M common/skylake/hw-gfx-gma-power_and_clocks.adb
1 file changed, 7 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/33/46633/1

diff --git a/common/skylake/hw-gfx-gma-power_and_clocks.adb b/common/skylake/hw-gfx-gma-power_and_clocks.adb
index 4c8b6ac..c860e1b 100644
--- a/common/skylake/hw-gfx-gma-power_and_clocks.adb
+++ b/common/skylake/hw-gfx-gma-power_and_clocks.adb
@@ -80,6 +80,8 @@
    LCPLL1_CTL_PLL_ENABLE               : constant := 1 * 2 ** 31;
    LCPLL1_CTL_PLL_LOCK                 : constant := 1 * 2 ** 30;

+   CNP_PWM_CGE_GATING_DISABLE          : constant := 1 * 2 ** 13;
+
    ----------------------------------------------------------------------------

CDCLK_CTL_CD_FREQ_SELECT_MASK       : constant := 3 * 2 ** 26;
@@ -333,6 +335,11 @@
         (Register    => Registers.LCPLL1_CTL,
          Mask        => LCPLL1_CTL_PLL_LOCK);

+      -- Display WA #1181 WaSouthDisplayDisablePWMCGEGating: cnp
+      Registers.Set_Mask
+        (Register    => Registers.PCH_DSPCLK_GATE_D,
+         Mask        => CNP_PWM_CGE_GATING_DISABLE);
+
       Get_Cur_CDClk (Config.CDClk);
       Get_Max_CDClk (Config.Max_CDClk);
       Set_CDClk (Config.Default_CDClk_Freq);