[coreboot-gerrit] Change in coreboot[master]: [WIP] soc/intel/denverton: MMCONF

[Kyösti Mälkki (Code Review)]

Attention is currently required from: Mariusz Szafrański, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Patrick Rudolph.
Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50667 )

Change subject: [WIP] soc/intel/denverton: MMCONF
......................................................................

[WIP] soc/intel/denverton: MMCONF

Change-Id: I85dd3306aae4fb9618127f32df063b91f4a5fbf7
Signed-off-by: Kyösti Mälkki 
---
M src/soc/intel/denverton_ns/acpi.c
M src/soc/intel/denverton_ns/include/soc/soc_util.h
M src/soc/intel/denverton_ns/soc_util.c
3 files changed, 18 insertions(+), 143 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/50667/1

diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c
index f455124..c859159 100644
--- a/src/soc/intel/denverton_ns/acpi.c
+++ b/src/soc/intel/denverton_ns/acpi.c
@@ -53,16 +53,29 @@

void soc_fill_gnvs(struct global_nvs *gnvs)
 {
+	uint32_t top_of_low_memory, tseg_memory;
+	uint64_t top_of_upper_memory;
+	struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT);
+
+	top_of_low_memory = pci_read_config32(dev, TOLUD) & MASK_TOLUD;
+	tseg_memory = pci_read_config32(dev, TSEGMB) & MASK_TSEGMB;
+
+	top_of_upper_memory = pci_read_config32(dev, TOUUD_HI) & MASK_TOUUD_HI;
+	top_of_upper_memory <<= 32;
+	top_of_upper_memory |= pci_read_config32(dev, TOUUD_LO) & MASK_TOUUD_LO;
+
    /* Top of Low Memory (start of resource allocation) */
    gnvs->tolm = (uintptr_t)cbmem_top();

/* MMIO Low/High & TSEG base and length */
-	gnvs->mmiob = (u32)get_top_of_low_memory();
-	gnvs->mmiol = (u32)(get_pciebase() - 1);
-	gnvs->mmiohb = (u64)get_top_of_upper_memory();
+	gnvs->mmiob = top_of_low_memory;
+	gnvs->mmiol = CONFIG_MMCONF_BASE_ADDRESS - 1;
+
+	gnvs->mmiohb = top_of_upper_memory;
    gnvs->mmiohl = (u64)(((u64)1 << CONFIG_CPU_ADDR_BITS) - 1);
-	gnvs->tsegb = (u32)get_tseg_memory();
-	gnvs->tsegl = (u32)(get_top_of_low_memory() - get_tseg_memory());
+
+	gnvs->tsegb = tseg_memory;
+	gnvs->tsegl = top_of_low_memory - tseg_memory;
 }

uint32_t soc_read_sci_irq_select(void)
diff --git a/src/soc/intel/denverton_ns/include/soc/soc_util.h b/src/soc/intel/denverton_ns/include/soc/soc_util.h
index 5b7a75d..c541aea 100644
--- a/src/soc/intel/denverton_ns/include/soc/soc_util.h
+++ b/src/soc/intel/denverton_ns/include/soc/soc_util.h
@@ -16,22 +16,15 @@

/* soc_util.c */
 #ifdef __SIMPLE_DEVICE__
-pci_devfn_t get_hostbridge_dev(void);
 pci_devfn_t get_lpc_dev(void);
 pci_devfn_t get_pmc_dev(void);
 pci_devfn_t get_smbus_dev(void);
 #else
-struct device *get_hostbridge_dev(void);
 struct device *get_lpc_dev(void);
 struct device *get_pmc_dev(void);
 struct device *get_smbus_dev(void);
 #endif

-uint32_t get_pciebase(void);
-uint32_t get_pcielength(void);
-uint32_t get_tseg_memory(void);
-uint32_t get_top_of_low_memory(void);
-uint64_t get_top_of_upper_memory(void);
 uint16_t get_pmbase(void);
 uint16_t get_tcobase(void);

diff --git a/src/soc/intel/denverton_ns/soc_util.c b/src/soc/intel/denverton_ns/soc_util.c
index d5b9b34..9219282 100644
--- a/src/soc/intel/denverton_ns/soc_util.c
+++ b/src/soc/intel/denverton_ns/soc_util.c
@@ -16,18 +16,6 @@
 #include <soc/systemagent.h>

#ifdef __SIMPLE_DEVICE__
-pci_devfn_t get_hostbridge_dev(void)
-{
-	return PCI_DEV(0, SA_DEV, SA_FUNC);
-}
-#else
-struct device *get_hostbridge_dev(void)
-{
-	return pcidev_on_root(SA_DEV, SA_FUNC);
-}
-#endif
-
-#ifdef __SIMPLE_DEVICE__
 pci_devfn_t get_lpc_dev(void)
 {
    return PCI_DEV(0, LPC_DEV, LPC_FUNC);
@@ -63,125 +51,6 @@
 }
 #endif

-uint32_t get_pciebase(void)
-{
-#ifdef __SIMPLE_DEVICE__
-	pci_devfn_t dev;
-#else
-	struct device *dev;
-#endif
-	u32 pciexbar_reg;
-
-	dev = get_hostbridge_dev();
-	if (!dev)
-		return 0;
-
-	pciexbar_reg = pci_read_config32(dev, PCIEXBAR);
-
-	if (!(pciexbar_reg & (1 << 0)))
-		return 0;
-
-	switch (pciexbar_reg & MASK_PCIEXBAR_LENGTH) {
-	case MASK_PCIEXBAR_LENGTH_256M:
-		pciexbar_reg &= MASK_PCIEXBAR_256M;
-		break;
-	case MASK_PCIEXBAR_LENGTH_128M:
-		pciexbar_reg &= MASK_PCIEXBAR_128M;
-		break;
-	case MASK_PCIEXBAR_LENGTH_64M:
-		pciexbar_reg &= MASK_PCIEXBAR_64M;
-		break;
-	default:
-		pciexbar_reg &= MASK_PCIEXBAR_256M;
-		break;
-	}
-
-	return pciexbar_reg;
-}
-
-uint32_t get_pcielength(void)
-{
-#ifdef __SIMPLE_DEVICE__
-	pci_devfn_t dev;
-#else
-	struct device *dev;
-#endif
-	u32 pciexbar_reg;
-
-	dev = get_hostbridge_dev();
-	if (!dev)
-		return 0;
-
-	pciexbar_reg = pci_read_config32(dev, PCIEXBAR);
-
-	if (!(pciexbar_reg & (1 << 0)))
-		return 0;
-
-	switch (pciexbar_reg & MASK_PCIEXBAR_LENGTH) {
-	case MASK_PCIEXBAR_LENGTH_256M:
-		pciexbar_reg = 256;
-		break;
-	case MASK_PCIEXBAR_LENGTH_128M:
-		pciexbar_reg = 128;
-		break;
-	case MASK_PCIEXBAR_LENGTH_64M:
-		pciexbar_reg = 64;
-		break;
-	default:
-		pciexbar_reg = 64;
-		break;
-	}
-
-	return pciexbar_reg;
-}
-
-uint32_t get_tseg_memory(void)
-{
-#ifdef __SIMPLE_DEVICE__
-	pci_devfn_t dev;
-#else
-	struct device *dev;
-#endif
-	dev = get_hostbridge_dev();
-
-	if (!dev)
-		return 0;
-
-	return pci_read_config32(dev, TSEGMB) & MASK_TSEGMB;
-}
-
-uint32_t get_top_of_low_memory(void)
-{
-#ifdef __SIMPLE_DEVICE__
-	pci_devfn_t dev;
-#else
-	struct device *dev;
-#endif
-	dev = get_hostbridge_dev();
-
-	if (!dev)
-		return 0;
-
-	return pci_read_config32(dev, TOLUD) & MASK_TOLUD;
-}
-
-uint64_t get_top_of_upper_memory(void)
-{
-#ifdef __SIMPLE_DEVICE__
-	pci_devfn_t dev;
-#else
-	struct device *dev;
-#endif
-	dev = get_hostbridge_dev();
-
-	if (!dev)
-		return 0;
-
-	return ((uint64_t)(pci_read_config32(dev, TOUUD_HI) & MASK_TOUUD_HI)
-		<< 32) +
-	       (uint64_t)(pci_read_config32(dev, TOUUD_LO) & MASK_TOUUD_LO);
-}
-
 uint16_t get_pmbase(void)
 {
 #ifdef __SIMPLE_DEVICE__