Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48308 )
Change subject: soc/amd/stoneyridge: order selected Kconfig options alphabetically ......................................................................
soc/amd/stoneyridge: order selected Kconfig options alphabetically
TEST=Timeless build doesn't change for amd/gardenia.
Change-Id: I5f1873111c07f6dc823b06654e463830d83acc9e Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/soc/amd/stoneyridge/Kconfig 1 file changed, 26 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/48308/1
diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index d672726..c1989e2 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -9,42 +9,42 @@
config CPU_SPECIFIC_OPTIONS def_bool y - select ARCH_ALL_STAGES_X86_32 - select X86_AMD_FIXED_MTRRS select ACPI_AMD_HARDWARE_SLEEP_VALUES + select ACPI_NO_SMI_GNVS + select ARCH_ALL_STAGES_X86_32 + select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select COLLECT_TIMESTAMPS_NO_TSC select DRIVERS_I2C_DESIGNWARE select GENERIC_GPIO_LIB select GENERIC_UDELAY - select IOAPIC select HAVE_CF9_RESET + select HAVE_SMI_HANDLER select HAVE_USBDEBUG_OPTIONS - select SOC_AMD_COMMON_BLOCK_SPI - select TSC_SYNC_LFENCE - select SOC_AMD_PI - select SOC_AMD_COMMON - select SOC_AMD_COMMON_BLOCK_IOMMU - select SOC_AMD_COMMON_BLOCK_ACPIMMIO - select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS - select SOC_AMD_COMMON_BLOCK_ACPI - select SOC_AMD_COMMON_BLOCK_AOAC - select SOC_AMD_COMMON_BLOCK_LPC - select SOC_AMD_COMMON_BLOCK_PCI - select SOC_AMD_COMMON_BLOCK_HDA - select SOC_AMD_COMMON_BLOCK_SATA - select SOC_AMD_COMMON_BLOCK_PI - select SOC_AMD_COMMON_BLOCK_PSP_GEN1 - select SOC_AMD_COMMON_BLOCK_CAR - select SOC_AMD_COMMON_BLOCK_S3 - select SOC_AMD_COMMON_BLOCK_SMBUS - select SOC_AMD_COMMON_BLOCK_SMI - select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH + select IOAPIC select PARALLEL_MP select PARALLEL_MP_AP_WORK - select HAVE_SMI_HANDLER - select SSE2 select RTC - select ACPI_NO_SMI_GNVS + select SOC_AMD_PI + select SOC_AMD_COMMON + select SOC_AMD_COMMON_BLOCK_ACPI + select SOC_AMD_COMMON_BLOCK_ACPIMMIO + select SOC_AMD_COMMON_BLOCK_AOAC + select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS + select SOC_AMD_COMMON_BLOCK_CAR + select SOC_AMD_COMMON_BLOCK_HDA + select SOC_AMD_COMMON_BLOCK_IOMMU + select SOC_AMD_COMMON_BLOCK_LPC + select SOC_AMD_COMMON_BLOCK_PCI + select SOC_AMD_COMMON_BLOCK_PI + select SOC_AMD_COMMON_BLOCK_PSP_GEN1 + select SOC_AMD_COMMON_BLOCK_S3 + select SOC_AMD_COMMON_BLOCK_SATA + select SOC_AMD_COMMON_BLOCK_SMBUS + select SOC_AMD_COMMON_BLOCK_SMI + select SOC_AMD_COMMON_BLOCK_SPI + select SSE2 + select TSC_SYNC_LFENCE + select X86_AMD_FIXED_MTRRS
config AMD_APU_STONEYRIDGE bool