[coreboot-gerrit] Change in ...coreboot[master]: mb/google/dragonegg: Patch for Audio Enabling

[Shelley Chen (Code Review)]

Hello Subrata Banik,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/29753

to review the following change.

Change subject: mb/google/dragonegg: Patch for Audio Enabling
......................................................................

mb/google/dragonegg: Patch for Audio Enabling

1. Enable Boot Beep support
2. Enable Audio over Speaker

Change-Id: Ia4843185dd79a35476c4f0fc0666ebaf3773db4c
Signed-off-by: Subrata Banik 
---
M src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb
M src/mainboard/google/dragonegg/variants/baseboard/gpio.c
2 files changed, 40 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/29753/1

diff --git a/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb b/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb
index b494ac9..051cc66 100644
--- a/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb
@@ -12,6 +12,11 @@
    	device lapic 0 on end
    end

+	register "EnableAzalia" = "1"
+	register "PchHdaDspEnable" = "1"
+	register "PchHdaAudioLinkSsp0" = "1"
+	register "PchHdaAudioLinkSsp1" = "1"
+
    # FSP configuration
    register "SaGv" = "SaGv_Disabled"
    register "SmbusEnable" = "1"
@@ -152,6 +157,15 @@
    		.speed_mhz = 1,
    		.early_init = 1,
    	},
+		.i2c[3] = {
+			.speed = I2C_SPEED_FAST,
+			.speed_config[0] = {
+				.speed = I2C_SPEED_FAST,
+				.scl_lcnt = 176,
+				.scl_hcnt = 95,
+				.sda_hold = 36,
+			}
+		},
    }"

device domain 0 on
@@ -237,7 +251,24 @@
    		end
    	end # I2C #1
    	device pci 15.2 on  end # I2C #2
-		device pci 15.3 on  end # I2C #3
+		device pci 15.3 on
+				chip drivers/i2c/max98373
+				register "vmon_slot_no" = "4"
+				register "imon_slot_no" = "5"
+				register "uid" = "0"
+				register "desc" = ""RIGHT SPEAKER AMP""
+				register "name" = ""MAXR""
+				device i2c 31 on end
+			end
+			chip drivers/i2c/max98373
+				register "vmon_slot_no" = "6"
+				register "imon_slot_no" = "7"
+				register "uid" = "1"
+				register "desc" = ""LEFT SPEAKER AMP""
+				register "name" = ""MAXL""
+				device i2c 32 on end
+			end
+		end # I2C #3
    	device pci 16.0 on  end # Management Engine Interface 1
    	device pci 16.1 off end # Management Engine Interface 2
    	device pci 16.2 off end # Management Engine IDE-R
diff --git a/src/mainboard/google/dragonegg/variants/baseboard/gpio.c b/src/mainboard/google/dragonegg/variants/baseboard/gpio.c
index acb3171..fddcc19 100644
--- a/src/mainboard/google/dragonegg/variants/baseboard/gpio.c
+++ b/src/mainboard/google/dragonegg/variants/baseboard/gpio.c
@@ -49,12 +49,20 @@
 /* USB_C0_SBU_2_DC */	PAD_CFG_GPO(GPP_E23, 0, DEEP),
 /* CNV_RF_RESET_N */		PAD_CFG_NF(GPP_F4, DN_20K, PWROK, NF1),
 /* CNV_CLKREQ0 */ 		PAD_CFG_NF(GPP_F5, DN_20K, PWROK, NF2),
+/* SPKR_IRQ_L */	PAD_CFG_GPI_APIC(GPP_F6, NONE, DEEP, LEVEL, NONE),
+/* SPKR_RST_L */ 	PAD_CFG_GPO(GPP_F19, 1, DEEP),
 /* SD_CD# */		PAD_CFG_GPI_GPIO_DRIVER(GPP_G5, UP_20K, DEEP),
 /* SD_WP */		PAD_CFG_NF(GPP_G7, DN_20K, DEEP, NF1),
+/* I2C3_SDA */		PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
+/* I2C3_SCL */		PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
 /* PCH_MEM_STRAP0 */		PAD_CFG_GPI(GPP_H12, DN_20K, PLTRST),
 /* PCH_MEM_STRAP1 */		PAD_CFG_GPI(GPP_H13, DN_20K, PLTRST),
 /* PCH_MEM_STRAP2 */		PAD_CFG_GPI(GPP_H14, DN_20K, PLTRST),
 /* PCH_MEM_STRAP3 */		PAD_CFG_GPI(GPP_H15, DN_20K, PLTRST),
+/* I2S0_SCLK */ 		PAD_CFG_GPO(GPP_R0, 1, DEEP),
+/* I2S0_SFRM */ 		PAD_CFG_GPO(GPP_R1, 1, DEEP),
+/* I2S0_TXD */ 		PAD_CFG_GPO(GPP_R2, 1, DEEP),
+/* I2S0_RXD */			PAD_CFG_GPI(GPP_R3, NONE, DEEP),
 };
 /* Early pad configuration in bootblock */
 static const struct pad_config early_gpio_table[] = {