[coreboot-gerrit] Change in coreboot[master]: soc/intel/broadwell: Add missing MCHBAR register definitions

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46364 )

Change subject: soc/intel/broadwell: Add missing MCHBAR register definitions
......................................................................

soc/intel/broadwell: Add missing MCHBAR register definitions

Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.

Change-Id: Ie8f369a704b833da86c2eb5864dffe2e8c4bb466
Signed-off-by: Angel Pons 
---
M src/soc/intel/broadwell/include/soc/systemagent.h
M src/soc/intel/broadwell/romstage/raminit.c
2 files changed, 11 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/46364/1

diff --git a/src/soc/intel/broadwell/include/soc/systemagent.h b/src/soc/intel/broadwell/include/soc/systemagent.h
index 5a52590..6d3ee31 100644
--- a/src/soc/intel/broadwell/include/soc/systemagent.h
+++ b/src/soc/intel/broadwell/include/soc/systemagent.h
@@ -87,7 +87,10 @@
 #define MCHBAR16(x)	*((volatile u16 *)(MCH_BASE_ADDRESS + (x)))
 #define MCHBAR32(x)	*((volatile u32 *)(MCH_BASE_ADDRESS + (x)))

-#define MCHBAR_PEI_VERSION	0x5034
+#define MAD_CHNL		0x5000
+#define MAD_DIMM(ch)		(0x5004 + 4 * (ch))
+
+#define MRC_REVISION		0x5034

#define MC_LOCK			0x50fc

@@ -133,6 +136,8 @@

#define BIOS_RESET_CPL		0x5da8

+#define MC_BIOS_DATA		0x5e04
+
 #define SAPMCTL			0x5f00

#define HDAUDRID		0x6008
diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c
index fb780cf..7b0e22f 100644
--- a/src/soc/intel/broadwell/romstage/raminit.c
+++ b/src/soc/intel/broadwell/romstage/raminit.c
@@ -30,12 +30,12 @@
    u32 addr_decoder_common, addr_decode_ch[2];
    int i;

-	addr_decoder_common = MCHBAR32(0x5000);
-	addr_decode_ch[0] = MCHBAR32(0x5004);
-	addr_decode_ch[1] = MCHBAR32(0x5008);
+	addr_decoder_common = MCHBAR32(MAD_CHNL);
+	addr_decode_ch[0] = MCHBAR32(MAD_DIMM(0));
+	addr_decode_ch[1] = MCHBAR32(MAD_DIMM(1));

printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n",
-	       (MCHBAR32(0x5e04) * 13333 * 2 + 50)/100);
+	       (MCHBAR32(MC_BIOS_DATA) * 13333 * 2 + 50)/100);
    printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n",
           addr_decoder_common & 3,
           (addr_decoder_common >> 2) & 3,
@@ -128,7 +128,7 @@
    	die("pei_data version mismatch\n");

/* Print the MRC version after executing the UEFI PEI stage. */
-	u32 version = MCHBAR32(MCHBAR_PEI_VERSION);
+	u32 version = MCHBAR32(MRC_REVISION);
    printk(BIOS_DEBUG, "MRC Version %d.%d.%d Build %d\n",
    	version >> 24, (version >> 16) & 0xff,
    	(version >> 8) & 0xff, version & 0xff);