[coreboot-gerrit] Change in coreboot[master]: soc/intel/xeon_sp/cpx: correct GSI bases for IO APICs

[Angel Pons (Code Review)]

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45941 )

Change subject: soc/intel/xeon_sp/cpx: correct GSI bases for IO APICs
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soc/intel/xeon_sp/cpx: correct GSI bases for IO APICs

With CPX-SP FSP, PCH IOAPIC handles the first 120(0x78) GSIs. Correct
the coreboot assignment of GSIs for IO APICs.

Without this patch, there are following target OS boot messages:
[    1.098771] IOAPIC[0]: apic_id 8, version 32, address 0xfec00000, GSI 0-119
[    1.099159] GSI range [24-31] for new IOAPIC conflicts with GSI[0-119]

After this patch, the boot messages are:
[    0.399498] IOAPIC[0]: apic_id 8, version 32, address 0xfec00000, GSI 0-119
[    0.399848] IOAPIC[1]: apic_id 9, version 32, address 0xfec01000, GSI 120-127

Also without this patch, there is boot stability issue. About one in
20 reboots, the target OS fails to boot with following failure:
[    4.325795] mce: [Hardware Error]: Machine check events logged
[    4.326597] mce: [Hardware Error]: CPU 0: Machine Check: 0 Bank 9: ee2000000003110a
[    4.327594] mce: [Hardware Error]: TSC 0 ADDR fe9e0000 MISC 228aa040101086
[    4.328596] mce: [Hardware Error]: PROCESSOR 0:5065b TIME 1601443875 SOCKET 0 APIC 0 microcode 700001d

The MCE error happens in bank 9. The Model specific error code
shows it is about SAD_ERR_WB_TO_MMIO error (doc 604926), which means
something goes wrong when cache write back to mmio. It is a generic
transaction type error in level 2.

Signed-off-by: Jonathan Zhang 
Change-Id: I45e941591300dad6d583a6dcb41f45e984753c07
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45941
Reviewed-by: Angel Pons 
Reviewed-by: Christian Walter 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/xeon_sp/cpx/acpi.c
1 file changed, 2 insertions(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, approved
  Christian Walter: Looks good to me, approved

diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c
index b9e261e..a1ebc4a 100644
--- a/src/soc/intel/xeon_sp/cpx/acpi.c
+++ b/src/soc/intel/xeon_sp/cpx/acpi.c
@@ -81,7 +81,8 @@
    int cur_index;
    struct iiostack_resource stack_info = {0};

-	int gsi_bases[] = { 0, 0x18, 0x20, 0x28, 0x30, 0x48, 0x50, 0x58, 0x60 };
+	/* With CPX-SP FSP, PCH IOAPIC is allocated with first 120 GSIs. */
+	int gsi_bases[] = { 0, 0x78, 0x80, 0x88, 0x90, 0x98, 0xA0, 0xA8, 0xB0 };
    int ioapic_ids[] = { 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0x10, 0x11, 0x12 };

/* Local APICs */