Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61106 )
Change subject: soc/intel/alderlake: Add GPP_I GPIO group for Alder Lake N SOC ......................................................................
soc/intel/alderlake: Add GPP_I GPIO group for Alder Lake N SOC
Add definitions for GPP_I GPIO group pins on Alder Lake N SOC and GPIO IRQ routing information.
GPP_I GPIO group belongs to GPIO community 1. Hence GPIO community 1 in Alder Lake N contains GPP_S, GPP_I, GPP_H, GPP_D GPIO groups.
GPIO groups 1-6 in Doc# 645550 Chapter 36 corresponds to GPIO communities 5-0 respectively.
BUG=b:213535859
Change-Id: Ia71a399c03cb7d098a381bd9439d448e8a620761 Signed-off-by: Krishna Prasad Bhat krishna.p.bhat.d@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/61106 Reviewed-by: Kangheui Won khwon@chromium.org Reviewed-by: Subrata Banik subratabanik@google.com Reviewed-by: Rizwan Qureshi rizwan.qureshi@intel.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/alderlake/gpio.c M src/soc/intel/alderlake/include/soc/gpio_defs.h M src/soc/intel/alderlake/include/soc/gpio_soc_defs.h M src/soc/intel/alderlake/include/soc/pmc.h 4 files changed, 301 insertions(+), 49 deletions(-)
Approvals: build bot (Jenkins): Verified Rizwan Qureshi: Looks good to me, approved Kangheui Won: Looks good to me, approved Subrata Banik: Looks good to me, approved
diff --git a/src/soc/intel/alderlake/gpio.c b/src/soc/intel/alderlake/gpio.c index 3d5af83..bf067b2 100644 --- a/src/soc/intel/alderlake/gpio.c +++ b/src/soc/intel/alderlake/gpio.c @@ -46,6 +46,15 @@ {GPP_B0, GPP_B23}, };
+#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) +static const struct pad_group adl_community1_groups[] = { + INTEL_GPP_BASE(GPP_S0, GPP_S0, GPP_S7, 96), /* GPP_S */ + INTEL_GPP_BASE(GPP_S0, GPP_I0, GPP_I19, 128), /* GPP_I */ + INTEL_GPP_BASE(GPP_S0, GPP_H0, GPP_H23, 160), /* GPP_H */ + INTEL_GPP_BASE(GPP_S0, GPP_D0, GPP_GSPI2_CLK_LOOPBK, 192), /* GPP_D */ + INTEL_GPP(GPP_S0, GPP_VGPIO_0, GPP_VGPIO_THC1), /* vGPIO */ +}; +#else static const struct pad_group adl_community1_groups[] = { INTEL_GPP_BASE(GPP_S0, GPP_S0, GPP_S7, 96), /* GPP_S */ INTEL_GPP_BASE(GPP_S0, GPP_H0, GPP_H23, 128), /* GPP_H */ @@ -53,6 +62,7 @@ INTEL_GPP(GPP_S0, GPP_CPU_RSVD_1, GPP_CPU_RSVD_24), /* GPP_CPU_RSVD */ INTEL_GPP(GPP_S0, GPP_VGPIO_0, GPP_VGPIO_37), /* vGPIO */ }; +#endif
static const struct vw_entries adl_community1_vw[] = { {GPP_D0, GPP_D19}, @@ -112,7 +122,8 @@ .vw_entries = adl_community0_vw, .num_vw_entries = ARRAY_SIZE(adl_community0_vw), }, - [COMM_1] = { /* GPP S, D, H */ + [COMM_1] = { /* GPP S, D, H for ADL-P/M + GPP S, I, D, H for ADL-N */ .port = PID_GPIOCOM1, .cpu_port = PID_CPU_GPIOCOM1, .first_pad = GPIO_COM1_START, @@ -126,7 +137,11 @@ .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) + .name = "GPP_SIHD", +#else .name = "GPP_SDH", +#endif .acpi_path = "\_SB.PCI0.GPIO", .reset_map = rst_map_gpp, .num_reset_vals = ARRAY_SIZE(rst_map_gpp), @@ -236,6 +251,9 @@ { PMC_GPP_T, GPP_T }, { PMC_GPP_A, GPP_A }, { PMC_GPP_S, GPP_S }, +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) + { PMC_GPP_I, GPP_I }, +#endif { PMC_GPP_H, GPP_H }, { PMC_GPP_D, GPP_D }, { PMC_GPD, GPD }, diff --git a/src/soc/intel/alderlake/include/soc/gpio_defs.h b/src/soc/intel/alderlake/include/soc/gpio_defs.h index e4f84ec..8602167 100644 --- a/src/soc/intel/alderlake/include/soc/gpio_defs.h +++ b/src/soc/intel/alderlake/include/soc/gpio_defs.h @@ -129,6 +129,29 @@ #define GPP_C22_IRQ 0x24 #define GPP_C23_IRQ 0x25
+#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) +/* Group D */ +#define GPP_D0_IRQ 0x40 +#define GPP_D1_IRQ 0x41 +#define GPP_D2_IRQ 0x42 +#define GPP_D3_IRQ 0x43 +#define GPP_D4_IRQ 0x44 +#define GPP_D5_IRQ 0x45 +#define GPP_D6_IRQ 0x46 +#define GPP_D7_IRQ 0x47 +#define GPP_D8_IRQ 0x48 +#define GPP_D9_IRQ 0x49 +#define GPP_D10_IRQ 0x4A +#define GPP_D11_IRQ 0x4B +#define GPP_D12_IRQ 0x4C +#define GPP_D13_IRQ 0x4D +#define GPP_D14_IRQ 0x4E +#define GPP_D15_IRQ 0x4F +#define GPP_D16_IRQ 0x50 +#define GPP_D17_IRQ 0x51 +#define GPP_D18_IRQ 0x52 +#define GPP_D19_IRQ 0x53 +#else /* Group D */ #define GPP_D0_IRQ 0x2C #define GPP_D1_IRQ 0x2D @@ -150,6 +173,7 @@ #define GPP_D17_IRQ 0x3D #define GPP_D18_IRQ 0x3E #define GPP_D19_IRQ 0x3F +#endif
/* Group E */ #define GPP_E0_IRQ 0x26 @@ -203,6 +227,55 @@ #define GPP_F22_IRQ 0x6C #define GPP_F23_IRQ 0x6D
+#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) +/* Group H */ +#define GPP_H0_IRQ 0x28 +#define GPP_H1_IRQ 0x29 +#define GPP_H2_IRQ 0x2A +#define GPP_H3_IRQ 0x2B +#define GPP_H4_IRQ 0x2C +#define GPP_H5_IRQ 0x2D +#define GPP_H6_IRQ 0x2E +#define GPP_H7_IRQ 0x2F +#define GPP_H8_IRQ 0x30 +#define GPP_H9_IRQ 0x31 +#define GPP_H10_IRQ 0x32 +#define GPP_H11_IRQ 0x33 +#define GPP_H12_IRQ 0x34 +#define GPP_H13_IRQ 0x35 +#define GPP_H14_IRQ 0x36 +#define GPP_H15_IRQ 0x37 +#define GPP_H16_IRQ 0x38 +#define GPP_H17_IRQ 0x39 +#define GPP_H18_IRQ 0x3A +#define GPP_H19_IRQ 0x3B +#define GPP_H20_IRQ 0x3C +#define GPP_H21_IRQ 0x3D +#define GPP_H22_IRQ 0x3E +#define GPP_H23_IRQ 0x3F + +/* Group I */ +#define GPP_I0_IRQ 0x74 +#define GPP_I1_IRQ 0x75 +#define GPP_I2_IRQ 0x76 +#define GPP_I3_IRQ 0x77 +#define GPP_I4_IRQ 0x18 +#define GPP_I5_IRQ 0x19 +#define GPP_I6_IRQ 0x1A +#define GPP_I7_IRQ 0x1B +#define GPP_I8_IRQ 0x1C +#define GPP_I9_IRQ 0x1D +#define GPP_I10_IRQ 0x1E +#define GPP_I11_IRQ 0x1F +#define GPP_I12_IRQ 0x20 +#define GPP_I13_IRQ 0x21 +#define GPP_I14_IRQ 0x22 +#define GPP_I15_IRQ 0x23 +#define GPP_I16_IRQ 0x24 +#define GPP_I17_IRQ 0x25 +#define GPP_I18_IRQ 0x26 +#define GPP_I19_IRQ 0x27 +#else /* Group H */ #define GPP_H0_IRQ 0x74 #define GPP_H1_IRQ 0x75 @@ -228,6 +301,7 @@ #define GPP_H21_IRQ 0x29 #define GPP_H22_IRQ 0x2A #define GPP_H23_IRQ 0x2B +#endif
/* Group R */ #define GPP_R0_IRQ 0x58 diff --git a/src/soc/intel/alderlake/include/soc/gpio_soc_defs.h b/src/soc/intel/alderlake/include/soc/gpio_soc_defs.h index b7216fa..80e656c 100644 --- a/src/soc/intel/alderlake/include/soc/gpio_soc_defs.h +++ b/src/soc/intel/alderlake/include/soc/gpio_soc_defs.h @@ -17,7 +17,12 @@ #define GPP_R INC(GPP_A) #define GPD INC(GPP_R) #define GPP_S INC(GPD) +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) +#define GPP_I INC(GPP_S) +#define GPP_H INC(GPP_I) +#else #define GPP_H INC(GPP_S) +#endif #define GPP_D INC(GPP_H) #define GPP_F 0xA #define GPP_C INC(GPP_F) @@ -35,9 +40,15 @@ * GPIOs are ordered monotonically increasing to match ACPI/OS driver. */ /* - * Group B - * PAD Start Number = 0 - * PAD End Number = 25 + * +------------------------------------+ + * | Group B | + * +------------------+---------+-------+ + * | | ADL-P/M | ADL-N | + * +------------------+---------+-------+ + * | Pad Start Number | 0 | 0 | + * +------------------+---------+-------+ + * | Pad End Number | 25 | 25 | + * +------------------+---------+-------+ */ #define GPP_B0 0 #define GPP_B1 INC(GPP_B0) @@ -67,9 +78,15 @@ #define GPP_B25 INC(GPP_B24) /* GSPI1_CLK_LOOPBK */
/* - * Group T - * PAD Start Number = 26 - * PAD End Number = 41 + * +------------------------------------+ + * | Group T | + * +------------------+---------+-------+ + * | | ADL-P/M | ADL-N | + * +------------------+---------+-------+ + * | Pad Start Number | 26 | 26 | + * +------------------+---------+-------+ + * | Pad End Number | 41 | 41 | + * +------------------+---------+-------+ */ #define GPP_T0 INC(GPP_B25) #define GPP_T1 INC(GPP_T0) @@ -89,9 +106,15 @@ #define GPP_T15 INC(GPP_T14)
/* - * Group A - * PAD Start Number = 42 - * PAD End Number = 66 + * +------------------------------------+ + * | Group A | + * +------------------+---------+-------+ + * | | ADL-P/M | ADL-N | + * +------------------+---------+-------+ + * | Pad Start Number | 42 | 42 | + * +------------------+---------+-------+ + * | Pad End Number | 66 | 66 | + * +------------------+---------+-------+ */ #define GPP_A0 INC(GPP_T15) #define GPP_A1 INC(GPP_A0) @@ -124,9 +147,15 @@ #define NUM_GPIO_COM0_PADS (GPIO_COM0_END - GPIO_COM0_START + 1)
/* - * Group S - * PAD Start Number = 67 - * PAD End Number = 74 + * +------------------------------------+ + * | Group S | + * +------------------+---------+-------+ + * | | ADL-P/M | ADL-N | + * +------------------+---------+-------+ + * | Pad Start Number | 67 | 67 | + * +------------------+---------+-------+ + * | Pad End Number | 74 | 74 | + * +------------------+---------+-------+ */ #define GPP_S0 INC(GPP_ESPI_CLK_LOOPBK) #define GPP_S1 INC(GPP_S0) @@ -137,12 +166,54 @@ #define GPP_S6 INC(GPP_S5) #define GPP_S7 INC(GPP_S6)
+#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) /* - * Group H - * PAD Start Number = 75 - * PAD End Number = 98 + * +------------------------------------+ + * | Group I | + * +------------------+---------+-------+ + * | | ADL-P/M | ADL-N | + * +------------------+---------+-------+ + * | Pad Start Number | NA | 75 | + * +------------------+---------+-------+ + * | Pad End Number | NA | 94 | + * +------------------+---------+-------+ */ +#define GPP_I0 INC(GPP_S7) +#define GPP_I1 INC(GPP_I0) +#define GPP_I2 INC(GPP_I1) +#define GPP_I3 INC(GPP_I2) +#define GPP_I4 INC(GPP_I3) +#define GPP_I5 INC(GPP_I4) +#define GPP_I6 INC(GPP_I5) +#define GPP_I7 INC(GPP_I6) +#define GPP_I8 INC(GPP_I7) +#define GPP_I9 INC(GPP_I8) +#define GPP_I10 INC(GPP_I9) +#define GPP_I11 INC(GPP_I10) +#define GPP_I12 INC(GPP_I11) +#define GPP_I13 INC(GPP_I12) +#define GPP_I14 INC(GPP_I13) +#define GPP_I15 INC(GPP_I14) +#define GPP_I16 INC(GPP_I15) +#define GPP_I17 INC(GPP_I16) +#define GPP_I18 INC(GPP_I17) +#define GPP_I19 INC(GPP_I18) + +/* + * +------------------------------------+ + * | Group H | + * +------------------+---------+-------+ + * | | ADL-P/M | ADL-N | + * +------------------+---------+-------+ + * | Pad Start Number | 75 | 95 | + * +------------------+---------+-------+ + * | Pad End Number | 98 | 118 | + * +------------------+---------+-------+ + */ +#define GPP_H0 INC(GPP_I19) +#else #define GPP_H0 INC(GPP_S7) +#endif #define GPP_H1 INC(GPP_H0) #define GPP_H2 INC(GPP_H1) #define GPP_H3 INC(GPP_H2) @@ -168,9 +239,15 @@ #define GPP_H23 INC(GPP_H22)
/* - * Group D - * PAD Start Number = 99 - * PAD End Number = 119 + * +------------------------------------+ + * | Group D | + * +------------------+---------+-------+ + * | | ADL-P/M | ADL-N | + * +------------------+---------+-------+ + * | Pad Start Number | 99 | 119 | + * +------------------+---------+-------+ + * | Pad End Number | 119 | 139 | + * +------------------+---------+-------+ */ #define GPP_D0 INC(GPP_H23) #define GPP_D1 INC(GPP_D0) @@ -194,10 +271,17 @@ #define GPP_D19 INC(GPP_D18) #define GPP_GSPI2_CLK_LOOPBK INC(GPP_D19)
+#if !CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) /* - * Reserved GPIOs - * PAD Start Number = 120 - * PAD End Number = 143 + * +------------------------------------+ + * | Reserved GPIOs | + * +------------------+---------+-------+ + * | | ADL-P/M | ADL-N | + * +------------------+---------+-------+ + * | Pad Start Number | 120 | NA | + * +------------------+---------+-------+ + * | Pad End Number | 143 | NA | + * +------------------+---------+-------+ */ #define GPP_CPU_RSVD_1 INC(GPP_GSPI2_CLK_LOOPBK) #define GPP_CPU_RSVD_2 INC(GPP_CPU_RSVD_1) @@ -225,11 +309,20 @@ #define GPP_CPU_RSVD_24 INC(GPP_CPU_RSVD_23)
/* - * Group VGPIO - * PAD Start Number = 144 - * PAD End Number = 170 + * +------------------------------------+ + * | Group VGPIO | + * +------------------+---------+-------+ + * | | ADL-P/M | ADL-N | + * +------------------+---------+-------+ + * | Pad Start Number | 144 | 140 | + * +------------------+---------+-------+ + * | Pad End Number | 170 | 168 | + * +------------------+---------+-------+ */ #define GPP_VGPIO_0 INC(GPP_CPU_RSVD_24) +#else +#define GPP_VGPIO_0 INC(GPP_GSPI2_CLK_LOOPBK) +#endif #define GPP_VGPIO_4 INC(GPP_VGPIO_0) #define GPP_VGPIO_5 INC(GPP_VGPIO_4) #define GPP_VGPIO_6 INC(GPP_VGPIO_5) @@ -257,16 +350,35 @@ #define GPP_VGPIO_36 INC(GPP_VGPIO_35) #define GPP_VGPIO_37 INC(GPP_VGPIO_36)
+#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) +#define GPP_VGPIO_THC0 INC(GPP_VGPIO_37) +#define GPP_VGPIO_THC1 INC(GPP_VGPIO_THC0) +#endif + #define GPIO_COM1_START GPP_S0 +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) +#define GPIO_COM1_END GPP_VGPIO_THC1 +#else #define GPIO_COM1_END GPP_VGPIO_37 +#endif #define NUM_GPIO_COM1_PADS (GPIO_COM1_END - GPIO_COM1_START + 1)
+#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) /* - * Group GPD - * PAD Start Number = 171 - * PAD End Number = 187 + * +------------------------------------+ + * | Group GPD | + * +------------------+---------+-------+ + * | | ADL-P/M | ADL-N | + * +------------------+---------+-------+ + * | Pad Start Number | 171 | 169 | + * +------------------+---------+-------+ + * | Pad End Number | 187 | 185 | + * +------------------+---------+-------+ */ +#define GPD0 INC(GPP_VGPIO_THC1) +#else #define GPD0 INC(GPP_VGPIO_37) +#endif #define GPD1 INC(GPD0) #define GPD2 INC(GPD1) #define GPD3 INC(GPD2) @@ -289,9 +401,15 @@ #define NUM_GPIO_COM2_PADS (GPIO_COM2_END - GPIO_COM2_START + 1)
/* - * PCIE VGPIO group - * PAD Start Number = 188 - * PAD End Number = 294 + * +------------------------------------+ + * | PCIE VGPIO Group | + * +------------------+---------+-------+ + * | | ADL-P/M | ADL-N | + * +------------------+---------+-------+ + * | Pad Start Number | 188 | 186 | + * +------------------+---------+-------+ + * | Pad End Number | 294 | 292 | + * +------------------+---------+-------+ */ #define GPP_CPU_RSVD_25 INC(GPD_DRAM_RESETB) #define GPP_CPU_RSVD_26 INC(GPP_CPU_RSVD_25) @@ -406,9 +524,15 @@ #define NUM_GPIO_COM3_PADS (GPIO_COM3_END - GPIO_COM3_START + 1)
/* - * Group C - * PAD Start Number = 295 - * PAD End Number = 318 + * +------------------------------------+ + * | Group C | + * +------------------+---------+-------+ + * | | ADL-P/M | ADL-N | + * +------------------+---------+-------+ + * | Pad Start Number | 295 | 293 | + * +------------------+---------+-------+ + * | Pad End Number | 318 | 316 | + * +------------------+---------+-------+ */ #define GPP_C0 INC(GPP_vGPIO_PCIE_83) #define GPP_C1 INC(GPP_C0) @@ -436,9 +560,15 @@ #define GPP_C23 INC(GPP_C22)
/* - * Group F - * PAD Start Number = 319 - * PAD End Number = 343 + * +------------------------------------+ + * | Group F | + * +------------------+---------+-------+ + * | | ADL-P/M | ADL-N | + * +------------------+---------+-------+ + * | Pad Start Number | 319 | 317 | + * +------------------+---------+-------+ + * | Pad End Number | 343 | 341 | + * +------------------+---------+-------+ */ #define GPP_F0 INC(GPP_C23) #define GPP_F1 INC(GPP_F0) @@ -467,9 +597,15 @@ #define GPP_F_CLK_LOOPBK INC(GPP_F23)
/* - * Group HVMOS - * PAD Start Number = 344 - * PAD End Number = 349 + * +------------------------------------+ + * | Group HVCMOS | + * +------------------+---------+-------+ + * | | ADL-P/M | ADL-N | + * +------------------+---------+-------+ + * | Pad Start Number | 344 | 342 | + * +------------------+---------+-------+ + * | Pad End Number | 349 | 347 | + * +------------------+---------+-------+ */ #define GPP_L_BKLTEN INC(GPP_F_CLK_LOOPBK) #define GPP_L_BKLTCTL INC(GPP_L_BKLTEN) @@ -479,9 +615,15 @@ #define GPP_MLK_RSTB INC(GPP_SYS_RESETB)
/* - * Group E - * PAD Start Number = 350 - * PAD End Number = 374 + * +------------------------------------+ + * | Group E | + * +------------------+---------+-------+ + * | | ADL-P/M | ADL-N | + * +------------------+---------+-------+ + * | Pad Start Number | 350 | 348 | + * +------------------+---------+-------+ + * | Pad End Number | 374 | 372 | + * +------------------+---------+-------+ */ #define GPP_E0 INC(GPP_MLK_RSTB) #define GPP_E1 INC(GPP_E0) @@ -514,9 +656,15 @@ #define NUM_GPIO_COM4_PADS (GPIO_COM4_END - GPIO_COM4_START + 1)
/* - * Group R - * PAD Start Number = 375 - * PAD End Number = 382 + * +------------------------------------+ + * | Group R | + * +------------------+---------+-------+ + * | | ADL-P/M | ADL-N | + * +------------------+---------+-------+ + * | Pad Start Number | 375 | 373 | + * +------------------+---------+-------+ + * | Pad End Number | 382 | 380 | + * +------------------+---------+-------+ */ #define GPP_R0 INC(GPP_E_CLK_LOOPBK) #define GPP_R1 INC(GPP_R0) @@ -528,9 +676,15 @@ #define GPP_R7 INC(GPP_R6)
/* - * Group SPI0 - * PAD Start Number = 383 - * PAD End Number = 390 + * +------------------------------------+ + * | Group SPI0 | + * +------------------+---------+-------+ + * | | ADL-P/M | ADL-N | + * +------------------+---------+-------+ + * | Pad Start Number | 383 | 381 | + * +------------------+---------+-------+ + * | Pad End Number | 390 | 388 | + * +------------------+---------+-------+ */ #define GPP_SPI0_IO_2 INC(GPP_R7) #define GPP_SPI0_IO_3 INC(GPP_SPI0_IO_2) diff --git a/src/soc/intel/alderlake/include/soc/pmc.h b/src/soc/intel/alderlake/include/soc/pmc.h index 2c02a2d..52cc0b5 100644 --- a/src/soc/intel/alderlake/include/soc/pmc.h +++ b/src/soc/intel/alderlake/include/soc/pmc.h @@ -112,8 +112,14 @@ #define PMC_GPP_R 0x3 #define PMC_GPD 0x4 #define PMC_GPP_S 0x5 +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) +#define PMC_GPP_I 0x6 +#define PMC_GPP_H 0x7 +#define PMC_GPP_D 0x8 +#else #define PMC_GPP_H 0x6 #define PMC_GPP_D 0x7 +#endif #define PMC_GPP_F 0xA #define PMC_GPP_C 0xB #define PMC_GPP_E 0xC