Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40525 )
Change subject: soc/mediatek/mt8183: Use term settings for high DRAM frequency ......................................................................
Patch Set 8:
(4 comments)
https://review.coreboot.org/c/coreboot/+/40525/7//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/40525/7//COMMIT_MSG@11 PS7, Line 11: should enable the term to improve the signal integrity.
this is from JEDEC STANDARD <JESD209-4B.pdf> […]
Ack
https://review.coreboot.org/c/coreboot/+/40525/8//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/40525/8//COMMIT_MSG@11 PS8, Line 11: . Reference: JEDEC STANDARD <JESD209-4B> 4.29 Command Bus Training
https://review.coreboot.org/c/coreboot/+/40525/3/src/soc/mediatek/mt8183/dra... File src/soc/mediatek/mt8183/dramc_init_setting.c:
https://review.coreboot.org/c/coreboot/+/40525/3/src/soc/mediatek/mt8183/dra... PS3, Line 1222: SELPH_DQS0_3200
we just use SELPH_DQS0_3200 for default value in dramc_setting() […]
Done
https://review.coreboot.org/c/coreboot/+/40525/8/src/soc/mediatek/mt8183/dra... File src/soc/mediatek/mt8183/dramc_init_setting.c:
https://review.coreboot.org/c/coreboot/+/40525/8/src/soc/mediatek/mt8183/dra... PS8, Line 1222: clrsetbits32 Can you add a comment before this line?
/* 3200 is the default value and may be changed in dramc_setting_DDRXXXX calls later */