Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36990 )
Change subject: soc/mediatek/mt8183: Use DDR clock to compute Tx delay cell ......................................................................
Patch Set 8:
(3 comments)
https://review.coreboot.org/c/coreboot/+/36990/7//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/36990/7//COMMIT_MSG@11 PS7, Line 11: helps improving
helps to improve
Done
https://review.coreboot.org/c/coreboot/+/36990/7/src/soc/mediatek/mt8183/dra... File src/soc/mediatek/mt8183/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/36990/7/src/soc/mediatek/mt8183/dra... PS7, Line 1608: clock_rate = 1792;
So delta = 4, but for 3600 where it is 8? Are these values documented in some datasheet?
According to MTK this is something trained by practice and just hard-coded. And yes it's 8 for 3600.
https://review.coreboot.org/c/coreboot/+/36990/7/src/soc/mediatek/mt8183/dra... PS7, Line 1621: dramc_dbg("bypass TX, clock_rate:%d\n", clock_rate);
Please add a space after the colon.
Done