[coreboot-gerrit] New patch to review for coreboot: a36bff5 southbridge/intel/bd82x6x: add option to disable hdmi audio codec

[Nicolas Reinecke]

Nicolas Reinecke ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8303

-gerrit

commit a36bff53e21a89a48a65b77bb3fd428f320b26be
Author: Nicolas Reinecke 
Date:   Thu Jan 29 23:43:06 2015 +0100

southbridge/intel/bd82x6x: add option to disable hdmi audio codec

Some Thinkpads like T420s or T520 with discrete GPU have only VGA
    and LVDS conntected to the IGP. For this devices is it usefull to
    have an option to disable the audio codec.

Change-Id: Iaa60b6d4c3c98ec9616ea0ef43913bbcf0d315da
    Signed-off-by: Nicolas Reinecke 
---
 src/southbridge/intel/bd82x6x/azalia.c | 23 +++++++++++------------
 src/southbridge/intel/bd82x6x/chip.h   |  2 ++
 2 files changed, 13 insertions(+), 12 deletions(-)

diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c
index bef88ab..ff958eb 100644
--- a/src/southbridge/intel/bd82x6x/azalia.c
+++ b/src/southbridge/intel/bd82x6x/azalia.c
@@ -228,6 +228,7 @@ static void codecs_init(struct device *dev, u32 base, u32 codec_mask)

static void azalia_init(struct device *dev)
 {
+	struct southbridge_intel_bd82x6x_config *config = dev->chip_info;
    u32 base;
    struct resource *res;
    u32 codec_mask;
@@ -267,22 +268,20 @@ static void azalia_init(struct device *dev)
    reg32 |= (1 << 31);
    pci_write_config32(dev, 0x120, reg32);

-	// Enable HDMI codec:
-	reg32 = pci_read_config32(dev, 0xc4);
-	reg32 |= (1 << 1);
-	pci_write_config32(dev, 0xc4, reg32);
+	if (!(config->azalia_hdmi_disable))) {
+		// Enable HDMI codec:
+		reg32 = pci_read_config32(dev, 0xc4);
+		reg32 |= (1 << 1);
+		pci_write_config32(dev, 0xc4, reg32);

-	reg8 = pci_read_config8(dev, 0x43);
-	reg8 |= (1 << 6);
-	pci_write_config8(dev, 0x43, reg8);
+		reg8 = pci_read_config8(dev, 0x43);
+		reg8 |= (1 << 6);
+		pci_write_config8(dev, 0x43, reg8);
+	}

/* Additional programming steps */
    reg32 = pci_read_config32(dev, 0xc4);
-	reg32 |= (1 << 13);
-	pci_write_config32(dev, 0xc4, reg32);
-
-	reg32 = pci_read_config32(dev, 0xc4);
-	reg32 |= (1 << 10);
+	reg32 |= (1 << 13) | (1 << 10);
    pci_write_config32(dev, 0xc4, reg32);

reg32 = pci_read_config32(dev, 0xd0);
diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h
index 290bb05..6182e44 100644
--- a/src/southbridge/intel/bd82x6x/chip.h
+++ b/src/southbridge/intel/bd82x6x/chip.h
@@ -89,6 +89,8 @@ struct southbridge_intel_bd82x6x_config {
    int docking_supported;

uint8_t pcie_hotplug_map[8];
+
+	uint8_t azalia_hdmi_disable;
 };

#endif				/* SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H */