Yu-Ping Wu has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81462?usp=email )
Change subject: soc/mediatek: Remove blank lines before '}' and after '{' ......................................................................
soc/mediatek: Remove blank lines before '}' and after '{'
Change-Id: I0ce2b61329efede1ba8a02446610e3eb635ceedc Signed-off-by: Elyes Haouas ehaouas@noos.fr Reviewed-on: https://review.coreboot.org/c/coreboot/+/81462 Reviewed-by: Yu-Ping Wu yupingso@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Yidi Lin yidilin@google.com Reviewed-by: Eric Lai ericllai@google.com --- M src/soc/mediatek/common/ddp.c M src/soc/mediatek/common/display.c M src/soc/mediatek/common/dp/dptx_hal.c M src/soc/mediatek/common/i2c.c M src/soc/mediatek/common/msdc.c M src/soc/mediatek/common/uart.c M src/soc/mediatek/mt8173/da9212.c M src/soc/mediatek/mt8173/dramc_pi_basic_api.c M src/soc/mediatek/mt8173/dramc_pi_calibration_api.c M src/soc/mediatek/mt8173/mt6391.c M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8186/devapc.c M src/soc/mediatek/mt8188/devapc.c M src/soc/mediatek/mt8188/include/soc/gpio.h M src/soc/mediatek/mt8192/devapc.c M src/soc/mediatek/mt8195/include/soc/gpio.h M src/soc/mediatek/mt8195/spm.c 18 files changed, 0 insertions(+), 31 deletions(-)
Approvals: Eric Lai: Looks good to me, approved Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, approved build bot (Jenkins): Verified
diff --git a/src/soc/mediatek/common/ddp.c b/src/soc/mediatek/common/ddp.c index 67e2fbf..7e2d373 100644 --- a/src/soc/mediatek/common/ddp.c +++ b/src/soc/mediatek/common/ddp.c @@ -46,7 +46,6 @@
void color_start(u32 width, u32 height) { - write32(&disp_color0->width, width); write32(&disp_color0->height, height); write32(&disp_color0->cfg_main, COLOR_BYPASS_ALL | COLOR_SEQ_SEL); diff --git a/src/soc/mediatek/common/display.c b/src/soc/mediatek/common/display.c index a5b0e6b..0dea58c 100644 --- a/src/soc/mediatek/common/display.c +++ b/src/soc/mediatek/common/display.c @@ -81,7 +81,6 @@ return -1; } } else { - struct panel_serializable_data *mipi_data = NULL;
if (panel->get_edid) { diff --git a/src/soc/mediatek/common/dp/dptx_hal.c b/src/soc/mediatek/common/dp/dptx_hal.c index b246c20..c46f457 100644 --- a/src/soc/mediatek/common/dp/dptx_hal.c +++ b/src/soc/mediatek/common/dp/dptx_hal.c @@ -324,7 +324,6 @@ void dptx_hal_setsdp_downcnt_init_inhblanking(struct mtk_dp *mtk_dp, u16 value) { mtk_dp_mask(mtk_dp, REG_3364_DP_ENCODER1_P0, value, 0xfff); - }
void dptx_hal_setsdp_downcnt_init(struct mtk_dp *mtk_dp, u16 value) diff --git a/src/soc/mediatek/common/i2c.c b/src/soc/mediatek/common/i2c.c index ab7b0de..886fb2a 100644 --- a/src/soc/mediatek/common/i2c.c +++ b/src/soc/mediatek/common/i2c.c @@ -472,7 +472,6 @@ base_step_cnt = step_cnt; if (best_mul == opt_div + clock_div_constraint) break; - }
if (!success) diff --git a/src/soc/mediatek/common/msdc.c b/src/soc/mediatek/common/msdc.c index 0d1dbb5..e7cd571 100644 --- a/src/soc/mediatek/common/msdc.c +++ b/src/soc/mediatek/common/msdc.c @@ -388,7 +388,6 @@ msdc_set_clock(host, ctrlr->request_hz);
msdc_set_buswidth(host, ctrlr->bus_width); - }
static void msdc_update_pointers(struct msdc_ctrlr *host) diff --git a/src/soc/mediatek/common/uart.c b/src/soc/mediatek/common/uart.c index 79ca072..4585fc0 100644 --- a/src/soc/mediatek/common/uart.c +++ b/src/soc/mediatek/common/uart.c @@ -111,7 +111,6 @@ write8(&uart_ptr->fcr, UART8250_FCR_FIFO_EN | UART8250_FCR_CLEAR_RCVR | UART8250_FCR_CLEAR_XMIT); - }
static void mtk_uart_tx_byte(unsigned char data) diff --git a/src/soc/mediatek/mt8173/da9212.c b/src/soc/mediatek/mt8173/da9212.c index 5028f18..2b118bf 100644 --- a/src/soc/mediatek/mt8173/da9212.c +++ b/src/soc/mediatek/mt8173/da9212.c @@ -47,7 +47,6 @@
if (ret) printk(BIOS_ERR, "%s failed\n", __func__); - }
void da9212_probe(uint8_t i2c_num) diff --git a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c index 10d03e0..e58ea53 100644 --- a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c @@ -154,7 +154,6 @@ static void pll_phase_adjust(u32 channel, struct mem_pll *mempll, int reg_offs) { switch (mempll->phase) { - case MEMPLL_INIT: /* initial phase: zero out RG_MEPLL(2,3,4)_(REF_DL,FB)_DL */ clrbits32(&ch[channel].ddrphy_regs->mempll[reg_offs], @@ -189,7 +188,6 @@ (idx + 2), mempll->phase, one_count, zero_count);
switch (mempll->phase) { - case MEMPLL_INIT: if ((one_count - zero_count) > JMETER_COUNT_N) { /* REF lag FBK */ @@ -243,7 +241,6 @@ JMETER_COUNT << JMETER_COUNTER_SHIFT);
while (1) { - for (i = 0; i < 3; i++) { if (!mempll[i].done) { pll_phase_adjust(channel, &mempll[i], (i + 2) * 3); @@ -317,7 +314,6 @@ udelay(100);
for (channel = 0; channel < CHANNEL_NUM; channel++) { - /* mempll_bias_en */ write32(&ch[channel].ddrphy_regs->mempll[3], 0xd << 28 | 0x1 << 6); diff --git a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c index fc5c58c..b9f11a0 100644 --- a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c @@ -751,7 +751,6 @@ max_taps = MAX_DQDLY_TAPS - 1;
for (i = 0; i < DATA_WIDTH_32BIT; i++) { - index = i / DQS_BIT_NUMBER;
if (i % DQS_BIT_NUMBER == 0) @@ -823,7 +822,6 @@ value += (curr_val << (4 * i));
switch (type) { - case TX_DQS: write32(&ch[channel].ddrphy_regs->padctl3, value); break; @@ -979,7 +977,6 @@
/* delay DQ from 0 to 15 to get the setup time */ for (dly = FIRST_DQ_DELAY; dly < MAX_DQDLY_TAPS; dly++) { - set_dly_factor(channel, STAGE_SETUP, type, dly); err_value = dram_k_perbit(channel);
@@ -1015,7 +1012,6 @@ /* delay DQS to get the hold time, dq_dly = dqs_dly = 0 is counted */ /* when we delay dq, so we set first dqs delay to 1 */ for (dly = (FIRST_DQS_DELAY + 1); dly < max_dqs_taps; dly++) { - set_dly_factor(channel, STAGE_HOLD, type, dly); err_value = dram_k_perbit(channel);
diff --git a/src/soc/mediatek/mt8173/mt6391.c b/src/soc/mediatek/mt8173/mt6391.c index 2186c06..f9a4629 100644 --- a/src/soc/mediatek/mt8173/mt6391.c +++ b/src/soc/mediatek/mt8173/mt6391.c @@ -78,7 +78,6 @@
pwrap_write_field(addr, vsel, 0x7, 5); pwrap_write_field(PMIC_RG_DIGLDO_CON5 + ldo * 2, 1, 1, 15); - }
void mt6391_enable_reset_when_ap_resets(void) @@ -362,7 +361,6 @@ pwrap_write_field(PMIC_RG_ANALDO_CON0, 0x3, 0x3, 3); /* For low power, VIO18 set sleep_en to HW mode */ pwrap_write_field(PMIC_RG_VIO18_CON18, 0x1, 0x1, 8); - }
static void mt6391_default_buck_voltage(void) diff --git a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c index d992371..0a4039b 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c @@ -289,7 +289,6 @@ clrsetbits32(&ch[chn].phy.r[rank].b[b].rxdvs[2], (0x3 << 30) | (0x1 << 28) | (0x1 << 23), (0x2 << 30) | (0x1 << 28) | (0x1 << 23)); - }
static void dramc_hw_dqs_gating_tracking(u8 chn) diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c index 5e4f01531..8b05667 100644 --- a/src/soc/mediatek/mt8183/emi.c +++ b/src/soc/mediatek/mt8183/emi.c @@ -537,7 +537,6 @@ dst_addr = (u8 *)&ch[chn].ao.shu[dst_shuffle] + offset; write32(dst_addr, read32(src_addr)); - } }
@@ -569,7 +568,6 @@ dst_addr = (u8 *)&ch[chn].phy.shu[dst_shuffle] + offset; write32(dst_addr, read32(src_addr)); - } } } diff --git a/src/soc/mediatek/mt8186/devapc.c b/src/soc/mediatek/mt8186/devapc.c index d831dcd..d32e62c 100644 --- a/src/soc/mediatek/mt8186/devapc.c +++ b/src/soc/mediatek/mt8186/devapc.c @@ -370,7 +370,6 @@
/* module, AP permission, N/A, SSPM permission, N/A */ static const struct apc_infra_peri_dom_4 mm_ao_sys0_devices[] = { - /* 0 */ DAPC_MM_AO_SYS0_ATTR("IP", NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION), diff --git a/src/soc/mediatek/mt8188/devapc.c b/src/soc/mediatek/mt8188/devapc.c index 6e47f705..6c585ba 100644 --- a/src/soc/mediatek/mt8188/devapc.c +++ b/src/soc/mediatek/mt8188/devapc.c @@ -1492,7 +1492,6 @@ for (j = 0; j < ARRAY_SIZE(infra_ao_sys2_devices[i].d_permission); j++) set_module_apc(base + SYS2_D0_APC_0, i, domain_map[j], infra_ao_sys2_devices[i].d_permission[j]); - }
static void set_peri_ao_apc(uintptr_t base) @@ -1516,7 +1515,6 @@ for (j = 0; j < ARRAY_SIZE(peri_ao_sys1_devices[i].d_permission); j++) set_module_apc(base + SYS1_D0_APC_0, i, domain_map[j], peri_ao_sys1_devices[i].d_permission[j]); - }
static void set_peri2_ao_apc(uintptr_t base) @@ -1527,7 +1525,6 @@ for (j = 0; j < ARRAY_SIZE(peri2_ao_sys0_devices[i].d_permission); j++) set_module_apc(base + SYS0_D0_APC_0, i, domain_map[j], peri2_ao_sys0_devices[i].d_permission[j]); - }
static void set_peri_par_ao_apc(uintptr_t base) @@ -1538,7 +1535,6 @@ for (j = 0; j < ARRAY_SIZE(peri_par_ao_sys0_devices[i].d_permission); j++) set_module_apc(base + SYS0_D0_APC_0, i, domain_map[j], peri_par_ao_sys0_devices[i].d_permission[j]); - }
static void dump_infra_ao_apc(uintptr_t base) @@ -1599,7 +1595,6 @@ for (i = 0; i < reg_max; i++) printk(BIOS_DEBUG, "[DEVAPC] (PERI2_AO_SYS0)D%d_APC_%d: %#x\n", d, i, read32(getreg_domain(base, SYS0_D0_APC_0, d, i))); - }
static void dump_peri_par_ao_apc(uintptr_t base) @@ -1716,7 +1711,6 @@ /* Master Domain */ SET32_BITFIELDS(getreg_domain(base, MAS_DOM_0, 0, 4), PCIE0_DOM, DOMAIN_2); - }
static void fmem_master_init(uintptr_t base) diff --git a/src/soc/mediatek/mt8188/include/soc/gpio.h b/src/soc/mediatek/mt8188/include/soc/gpio.h index 8767e0f..916cf84 100644 --- a/src/soc/mediatek/mt8188/include/soc/gpio.h +++ b/src/soc/mediatek/mt8188/include/soc/gpio.h @@ -44,7 +44,6 @@ })
enum { - PIN(0, GPIO00, 0, 6, 0x31, 0xe0, TP_GPIO0_AO, SPIM5_CSB, UTXD1, DMIC3_CLK, I2SIN_MCK, I2SO2_MCK, DBG_MON_A0), diff --git a/src/soc/mediatek/mt8192/devapc.c b/src/soc/mediatek/mt8192/devapc.c index 1fdc519..96bd2bd 100644 --- a/src/soc/mediatek/mt8192/devapc.c +++ b/src/soc/mediatek/mt8192/devapc.c @@ -46,7 +46,6 @@ TWO_BIT_DOM_REMAP_2, MAS_DOMAIN_1, TWO_BIT_DOM_REMAP_3, MAS_DOMAIN_3, TWO_BIT_DOM_REMAP_4, MAS_DOMAIN_1); - }
static void peri_master_init(uintptr_t base) diff --git a/src/soc/mediatek/mt8195/include/soc/gpio.h b/src/soc/mediatek/mt8195/include/soc/gpio.h index 60f3af1..02c3580 100644 --- a/src/soc/mediatek/mt8195/include/soc/gpio.h +++ b/src/soc/mediatek/mt8195/include/soc/gpio.h @@ -37,7 +37,6 @@ })
enum { - PIN(0, GPIO_00, 1, 0, 0x23, 0x60, TP_GPIO0_AO, MSDC2_CMD, TDMIN_MCK, CLKM0, PERSTN_1, IDDIG_1P, DMIC4_CLK), diff --git a/src/soc/mediatek/mt8195/spm.c b/src/soc/mediatek/mt8195/spm.c index 457c019..01df38d 100644 --- a/src/soc/mediatek/mt8195/spm.c +++ b/src/soc/mediatek/mt8195/spm.c @@ -467,7 +467,6 @@ SPM_DVFSRC_ENABLE_LSB, 1); write32(&mtk_spm->spm_dvfs_level, SPM_DVFS_LEVEL_DEF); write32(&mtk_spm->spm_dvs_dfs_level, SPM_DVS_DFS_LEVEL_DEF); - }
void spm_reset_and_init_pcm(void)