Bora Guvendik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32992
Change subject: soc/intel/cannonlake: Add ability to disable Heci1 ......................................................................
soc/intel/cannonlake: Add ability to disable Heci1
Decide if HECI1 should be hidden prior to boot to OS.
BUG=none TEST=Boot to OS, verify if Heci1 is disabled
Change-Id: I7c63316c8b04fb101d34064daac5ba4fdc05a63c Signed-off-by: Bora Guvendik bora.guvendik@intel.com --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/cannonlake/romstage/fsp_params.c 3 files changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/32992/1
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 0d51c1c..6bea8fe 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -421,6 +421,7 @@ * Bit 0: MISCCFG_GPDLCGEN */ uint8_t gpio_pm[TOTAL_GPIO_COMM]; + uint8_t Heci1Disabled; };
typedef struct soc_intel_cannonlake_config config_t; diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index dd93882..7dc1dd0 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -341,6 +341,7 @@ params->ScsUfsEnabled = dev->enabled;
params->Heci3Enabled = config->Heci3Enabled; + params->Heci1Disabled = config->Heci1Disabled; params->Device4Enable = config->Device4Enable;
/* VrConfig Settings for 5 domains diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 6e492bb..365fb9f 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -25,7 +25,6 @@ #include <vendorcode/google/chromeos/chromeos.h>
#include "../chip.h" - static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config) { unsigned int i;