Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31372 )
Change subject: soc/amd: Add support to soc merlinfalcon ......................................................................
Patch Set 1:
(2 comments)
Patch Set 1:
(1 comment)
This change is ready for review.
https://review.coreboot.org/#/c/31372/1/src/soc/amd/stoneyridge/include/soc/... File src/soc/amd/stoneyridge/include/soc/pci_devs.h:
https://review.coreboot.org/#/c/31372/1/src/soc/amd/stoneyridge/include/soc/... PS1, Line 118: #define HT_DEVID_CZ 0x1570 : #define HT_DEVID_ST 0x15b0
Skip the graphics. Yes, HDA should be added. […]
This is what I'm planning to do... do you have a different idea? /* HD Audio 0 */ #define HDA0_DEV 0x1 #define HDA0_FUNC 1 #if IS_ENABLED(CONFIG_STONEYRIDGE_CPU_MF) #define HDA0_DEVID PCI_DEVICE_ID_AMD_15H_MODEL_606F_HDA #else #define HDA0_DEVID PCI_DEVICE_ID_AMD_15H_MODEL_707F_HDA #endif #define HDA0_DEVFN PCI_DEVFN(HDA0_DEV, HDA0_FUNC) #define SOC_HDA0_DEV _SOC_DEV(HDA0_DEV, HDA0_FUNC)
https://review.coreboot.org/#/c/31372/1/src/soc/amd/stoneyridge/include/soc/... File src/soc/amd/stoneyridge/include/soc/southbridge.h:
https://review.coreboot.org/#/c/31372/1/src/soc/amd/stoneyridge/include/soc/... PS1, Line 189: #define OSCOUT2_CLK_OUTPUT_ENB BIT(7) /* 0 = Enabled, 1 = Disabled */
This is not about the core(s). They're auxiliary clocks from the FCH to external devices. […]
Ok, I was not aware of this difference between Intel and AMD hyperthread. I have worked mostly with Intel chips throughout my career. I only ever did 2 AMD CPU, both a long time ago(12y and 17y).